[T10] SPL-5 proposal to mandate transmitting three IDENTIFY address frames

Tim.Symons at microchip.com Tim.Symons at microchip.com
Wed Sep 11 08:53:45 PDT 2019


For attention of SAS device interface implementers.

Proposal 19-093r1 has been posted to the reflector for review in a future T10 CAP meeting.

A copy of the overview is included in this E-mail, and a clause for review to highlight:
Overview
In SPL-3, the Start DWS message occurs during TRAIN_RX, such that the SP_DWS should be in sync by PHY_READY and therefore able to accept dwords and send them to the link. If the other link has started sending the Identify before this link is PHY_READY, the data words from the Identify are accepted.
However, in SPL-4, the Start PS is not issued until PHY_READY. By that time, the other link might have started sending the IDENTIFY address frame(s). Those address frames are then lost (they are not passed to the link layer) since sync might not have been achieved.
It is not an issue if the other link sends three IDENTIFY address frames. But if it is configured to send only one (as in cases of SAS compliance tests), it could be missed, resulting in the Receive Identify Timeout timer expiring and a phy reset sequence.

The SPL-5 currently defines that three IDENTIFY address frame transmission should be sent, this proposal is for three IDENTIFY address frame transmission shall be sent.

Existing text that may make this proposal unnecessary (to be debated):

6.12.5.3 SL_IR_IRC2:Wait state
6.12.5.3.1 State description
This state ensures that an IDENTIFY address frame has been received by the SL_IR_RIF state machine and that an IDENTIFY address frame has been transmitted by the SL_IR_TIR state machine before enabling the rest of the link layer. The IDENTIFY address frames may be transmitted and received on the physical link in any order.

Editors Note : Does the highlighted text ensure that an identification sequence cannot fail to detect the first IDENTIFY address frame  ?  - Need to review before committing to changes in this proposal


Regards
Tim.


Tim Symons | Storage Architect
Microchip Technology Inc.
8555 Baxter Place, Burnaby, BC V5A 4V7. Canada
Tel. 604 415 6000
Email: Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>

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