[T10] [SAS] Request for clarification of scrambled IDLE Segment

Tim.Symons at microchip.com Tim.Symons at microchip.com
Wed Sep 4 15:14:29 PDT 2019


You are correct- the scrambled idle segment sequence only contains those values immediately after a PACKET_SYNC, so I think it is better to revise the table so that the header is 11b:

[cid:image004.png at 01D5632C.7DBB85D0]
>From our initial query on question 1) and 3) is still unanswered, can you help us to get insight on those ?
-          Our main confusion from specification - Is there any possibility that just after Train_RX-SNW/SP15_PHY_READY state transition scrambled idle segment may arrive (transmitted) or not ?
-          Is there any implications faced by transmitter or receiver - if first SPL packet after PACKET_SYNC is scrambled IDLE segment (not IDLE frame segment) ?

There should be no reason for a scrambled IDLE segment to be sent or received after a link reset event (Train_RX), as there is no synchronization established at that time.
If one was transmitted or received, the scrambled Idle segment is a deleatable primitive and would be ignored at that time, so there would be no implications.

Referencing SPL5r08:
When the SAS PHY Layer state machine (SP) enters SP15:SAS_PHY_Ready state is sends a Start_PS message to the SP_PS state machine:
5.14.4.10 SP15:SAS_PHY_Ready state
5.14.4.10.1 State description
This state waits for:
a) a COMINIT Detected message;
b) a DWS Lost message;
c) a DWS Reset message;
d) a PS Reset message; or
e) a Manage Phy Power Conditions request.
Upon entry into this state, this state shall:
a) send a Phy Layer Ready (SAS) confirmation to the link layer; and
b) if the SP transmitter is transmitting at:
A) 1.5 Gbit/s, then set the ResetStatus state machine variable to G1;
B) 3 Gbit/s, then set the ResetStatus state machine variable to G2;
C) 6 Gbit/s, then set the ResetStatus state machine variable to G3;
D) 12 Gbit/s, then set the ResetStatus state machine variable to G4; or
E) 22.5 Gbit/s, then:
a) send an Enable APTA confirmation to the management application layer;
b) send an Enable APTA message to the PAPTA state machines;
c) set the ResetStatus state machine variable to G5;
d) send a Start PS message to the SP_PS state machine;
e) send a Stop DWS message to the SP_DWS state machine; and
f) initialize and start the Scrambler Initialization timer.
When the Scrambler Initialization timer expires, this state shall:
1) send a Transmit PACKET_SYNC message to the SP transmitter; and
2) initialize and start the Scrambler Initialization timer.
<.....>
The SP_PS state machine synchronizes the packets, and the receiver ignores scrambled dwords.

5.16 SP_PS (phy layer SPL packet synchronization) state machine
5.16.2 SP_PS receiver
The SP_PS receiver shall discard all dwords received within an SPL packet that contains a scrambled idle
segment (i.e., scrambled dwords).



From: Deep Mehta <deep at cadence.com>
Sent: Wednesday, September 4, 2019 1:38 AM
To: Tim Symons - C33374 <Tim.Symons at microchip.com>; t10 at t10.org
Cc: Gurudatta Mewundi <gmewundi at cadence.com>; Lana Chan <lana at cadence.com>
Subject: RE: [SAS] Request for clarification of scrambled IDLE Segment


External E-Mail


Hi Tim,

Any thought/update here ?

Regards,
Deep

From: Deep Mehta
Sent: Sunday, September 1, 2019 4:11 PM
To: Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>; t10 at t10.org<mailto:t10 at t10.org>
Cc: Gurudatta Mewundi <gmewundi at cadence.com<mailto:gmewundi at cadence.com>>; Lana Chan <lana at cadence.com<mailto:lana at cadence.com>>
Subject: RE: [SAS] Request for clarification of scrambled IDLE Segment

Hi Tim,

Thanks for the response.

Referring to your suggestion in description,
Scrambled idle segment (e.g., immediately following a PACKET_SYNC SPL frame segment):

Question 1: Input Packet contains Dword0 as 0x6CBD9498h ; Dword1 0x53C6D8CEh ; Dword2 as 0x506A75C1h and Dword3 as 0x044FC307h (as shown in below figure)

[cid:image005.jpg at 01D56333.7182B110]


-          These Dwords values are only possible after initialization/re-initialization of scrambler as per specification reference Table F.3 8-bit pattern generator values produced after initialization of scrambler by PACKET_SYNC
-          So, it is not possible to have these "scrambled" values after a SPL frame segment (as here, scrambler will be already advance results in different input packet values)
-          Can you please clarify on this ?

Moving further, from initial query mail our doubt on 2) regarding DwordHeader field expectation is clarified from your answer.

>From our initial query on question 1) and 3) is still unanswered, can you help us to get insight on those ?
-          Our main confusion from specification - Is there any possibility that just after Train_RX-SNW/SP15_PHY_READY state transition scrambled idle segment may arrive (transmitted) or not ?
-          Is there any implications faced by transmitter or receiver - if first SPL packet after PACKET_SYNC is scrambled IDLE segment (not IDLE frame segment) ?

Thanks.

Regards,
Deep
From: Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com> <Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>>
Sent: Saturday, August 31, 2019 12:25 AM
To: Deep Mehta <deep at cadence.com<mailto:deep at cadence.com>>; t10 at t10.org<mailto:t10 at t10.org>
Cc: Gurudatta Mewundi <gmewundi at cadence.com<mailto:gmewundi at cadence.com>>; Lana Chan <lana at cadence.com<mailto:lana at cadence.com>>
Subject: RE: [SAS] Request for clarification of scrambled IDLE Segment

EXTERNAL MAIL
Annexes contain informative examples that are not mandatory definitions.

I agree with your observation that the Scrambled Idle segment example illustrated in Table D.1 should have the header field set to 11b.
I think the easiest way to correct the table will be to change the description:

                Scrambled idle segment (e.g., immediately following a PACKET_SYNC SPL frame segment):

In cases such as this, where an informative annex appears to be incorrect, you should always defer to the normative specification text.

From: Deep Mehta <deep at cadence.com<mailto:deep at cadence.com>>
Sent: Thursday, August 29, 2019 2:32 AM
To: t10 at t10.org<mailto:t10 at t10.org>; Tim Symons - C33374 <Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>>
Cc: Gurudatta Mewundi <gmewundi at cadence.com<mailto:gmewundi at cadence.com>>; Lana Chan <lana at cadence.com<mailto:lana at cadence.com>>
Subject: RE: [SAS] Request for clarification of scrambled IDLE Segment


External E-Mail


Hi Tim,

Any thought ?
We highly appreciate your help here.

Thanks.

Regards,
Deep

From: Lana Chan
Sent: Friday, August 23, 2019 11:55 PM
To: t10 at t10.org<mailto:t10 at t10.org>
Cc: Deep Mehta <deep at cadence.com<mailto:deep at cadence.com>>; Gurudatta Mewundi <gmewundi at cadence.com<mailto:gmewundi at cadence.com>>; Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>
Subject: [SAS] Request for clarification of scrambled IDLE Segment

Hello,
Can you please help clarify a few questions regarding the scrambled IDL segment for packet mode (SPL4)

As per Annexure Table D.1 - Example forward error correction coding results , it is mentioned - Scrambled idle segment (e.g., immediately following a PACKET_SYNC)

[cid:image003.jpg at 01D5632B.DD9746C0]

Questions:
========
1)      Referring to table D.1 - Is it possible for PHY transmitter to transmit Scrambled IDLE segment just after PACKET_SYNC ? Specifically, just after Train_RX-SNW/SP15_PHY_READY state transition? As per section 6.6 Idle physical links



Phys shall transmit idle dwords if there are no other dwords to transmit


2)      For periodic PACKET_SYNC transmission condition (not at SP15_PHY_READY state transition), how it is possible to have Scrambled Idle segment DwordHeader as "00b" ?  Since the last bit of  the last transferred bit of the PACKET_SYNC is '0' (as shown below diagram and table D.1), that SPL_PACKET_HEADER must be "11b". This is described in 6.8.3 in SPL4
3)      What is the implications for transmitter, if it transmit scrambled IDLE segment just at SP15_PHY_READY state transition condition (as first SPL packet) and then transmit IDLE Dword packet?


Thanks in advance
Lana

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