[T10] [SAS] Request for clarification of scrambled IDLE Segment

Tim.Symons at microchip.com Tim.Symons at microchip.com
Fri Aug 30 11:55:25 PDT 2019

Annexes contain informative examples that are not mandatory definitions.

I agree with your observation that the Scrambled Idle segment example illustrated in Table D.1 should have the header field set to 11b.
I think the easiest way to correct the table will be to change the description:

                Scrambled idle segment (e.g., immediately following a PACKET_SYNC SPL frame segment):

In cases such as this, where an informative annex appears to be incorrect, you should always defer to the normative specification text.

From: Deep Mehta <deep at cadence.com>
Sent: Thursday, August 29, 2019 2:32 AM
To: t10 at t10.org; Tim Symons - C33374 <Tim.Symons at microchip.com>
Cc: Gurudatta Mewundi <gmewundi at cadence.com>; Lana Chan <lana at cadence.com>
Subject: RE: [SAS] Request for clarification of scrambled IDLE Segment

External E-Mail

Hi Tim,

Any thought ?
We highly appreciate your help here.



From: Lana Chan
Sent: Friday, August 23, 2019 11:55 PM
To: t10 at t10.org<mailto:t10 at t10.org>
Cc: Deep Mehta <deep at cadence.com<mailto:deep at cadence.com>>; Gurudatta Mewundi <gmewundi at cadence.com<mailto:gmewundi at cadence.com>>; Tim.Symons at microchip.com<mailto:Tim.Symons at microchip.com>
Subject: [SAS] Request for clarification of scrambled IDLE Segment

Can you please help clarify a few questions regarding the scrambled IDL segment for packet mode (SPL4)

As per Annexure Table D.1 - Example forward error correction coding results , it is mentioned - Scrambled idle segment (e.g., immediately following a PACKET_SYNC)

[cid:image001.jpg at 01D55F29.CEEE4FC0]

1)      Referring to table D.1 - Is it possible for PHY transmitter to transmit Scrambled IDLE segment just after PACKET_SYNC ? Specifically, just after Train_RX-SNW/SP15_PHY_READY state transition? As per section 6.6 Idle physical links

Phys shall transmit idle dwords if there are no other dwords to transmit

2)      For periodic PACKET_SYNC transmission condition (not at SP15_PHY_READY state transition), how it is possible to have Scrambled Idle segment DwordHeader as "00b" ?  Since the last bit of  the last transferred bit of the PACKET_SYNC is '0' (as shown below diagram and table D.1), that SPL_PACKET_HEADER must be "11b". This is described in 6.8.3 in SPL4
3)      What is the implications for transmitter, if it transmit scrambled IDLE segment just at SP15_PHY_READY state transition condition (as first SPL packet) and then transmit IDLE Dword packet?

Thanks in advance

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