[T10] [SAS] Request for clarification of scrambled IDLE Segment

Lana Chan lana at cadence.com
Fri Aug 23 11:25:08 PDT 2019

Can you please help clarify a few questions regarding the scrambled IDL segment for packet mode (SPL4)

As per Annexure Table D.1 - Example forward error correction coding results , it is mentioned - Scrambled idle segment (e.g., immediately following a PACKET_SYNC)

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  1.  Referring to table D.1 - Is it possible for PHY transmitter to transmit Scrambled IDLE segment just after PACKET_SYNC ? Specifically, just after Train_RX-SNW/SP15_PHY_READY state transition? As per section 6.6 Idle physical links

Phys shall transmit idle dwords if there are no other dwords to transmit

  1.  For periodic PACKET_SYNC transmission condition (not at SP15_PHY_READY state transition), how it is possible to have Scrambled Idle segment DwordHeader as "00b" ?  Since the last bit of  the last transferred bit of the PACKET_SYNC is '0' (as shown below diagram and table D.1), that SPL_PACKET_HEADER must be "11b". This is described in 6.8.3 in SPL4
  2.  What is the implications for transmitter, if it transmit scrambled IDLE segment just at SP15_PHY_READY state transition condition (as first SPL packet) and then transmit IDLE Dword packet?

Thanks in advance

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