Ultra SCSI proposal

Gerry Houlder Gerry_Houlder at notes.seagate.com
Sun Sep 6 23:24:59 PDT 2015


_Date: 02-03-94 05:37:49 AM
_To: scsireflector
_Recipient: scsi at WichitaKS.NCR.COM@internet
_From: Gerry Houlder at SEAGATE
_Subject: re: Ultra SCSI proposal

I have studied the following timings from the Ultra SCSI proposal sent to the 
reflector within the last 2 days:

| Receive Assertion Period. . . . .   [11 ns]      22 ns       70 ns       
n/a    
| Receive Hold Time (note 2). . . .   [12 ns]      25 ns       25 ns       
n/a    
| Receive Negation Period . . . . .   [11 ns]      22 ns       70 ns       n/a 
        :
| System Deskew Delay . . . . . . .    20 ns       20 ns       45 ns       45 
ns 

The "System Deskew Delay" is defined as:

 The minimum time that a device should wait after receiving an SCSI signal
 to ensure that any signals transmitted at the same time are valid.

I believe this has to mean that the system deskew delay must be shorter than 
the narrowest pulse that can exist on the bus. The "receive assertion period" 
and the "receive negation period" are the narrowest pulses that can exist on 
the bus. For fast transfers, the system deskew delay is only 2 ns less than the 
narrowest pulse (this gives silicon only a 2 ns margin to determine the 
difference between a glitch and a real pulse) but for ultra 1 the system deskew 
delay is 9 ns longer than the narrowest valid pulse!

The system deskew delay must be decreased to 9 ns. This allows silicon vendors 
the same 2 ns margin that is present for fast transfers (which must be enough, 
or we would have heard complaints about the fast timing numbers, RIGHT?).

I will not be able to attend the March 2 Ultra SCSI meeting, but hope that the 
attendees will address this issue.

--
Gerry Houlder (Gerry_Houlder at notes.seagate.com)
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