ADC: WP bit in RMC logical unit subpage
Kevin D Butt
kdbutt at us.ibm.com
Mon Mar 2 11:20:26 PST 2009
Formatted message: <a href="http://www.t10.org/cgi-bin/ac.pl?t=r&f=r0903020_f.htm">HTML-formatted message</a>
Attachment #1: <a href="http://www.t10.org/cgi-bin/ac.pl?t=r&f=r0903020_nameless-3040-3.gif">nameless-3040-3.gif</a>
ADC-3 dictates that the WP bit of the RMC logical unit subpage shall be
cleared on unload. Is the intent that the WP bit in the mode page is
cleared so it will not be active for the next load. In thinking through
this scenario, I wonder if the wording in ADC has some issues that need
resolved. For example, which state does "unloaded" mean?
We need to be explicit about which state is meant. Where this really
matters is when does MAM not get a write protect? I suspect the intent is
unload state g.
To be explicit about scenarios where I think the standard is unclear, here
is a list.
1) The volume is mounted and WP bit is set to one. Then the volume is
unloaded to unload state e). A Write Attribute is attempted on MAM.
Should there be a Check Condition (i.e., what is the value of the WP bit)?
2) After #1 the volume is then mounted and threaded and comes ready. What
is the value of the WP bit?
I think that the intent is to protect the currently mounted volume through
the entire time that it might be altered. Therefore, I think that MAM
should also be protected until it is no longer accessible (i.e., until
unload state is beyond f - that would g or h depending on technology).
I also believe that the intent of the clearing the WP bit is to make sure
that the next loaded volume is not inadvertently write protected. This
clearing would not apply to a volume that was unmounted to the hold point
(i.e., MAM accessible) and then mounted again. This volume should still
be write protected.
Does anybody disagree with this?
Thanks,
Kevin D. Butt
SCSI & Fibre Channel Architect, Tape Firmware
MS 6TYA, 9000 S. Rita Rd., Tucson, AZ 85744
Tel: 520-799-5280
Fax: 520-799-2723 (T/L:321)
Email address: kdbutt at us.ibm.com
More information about the T10
mailing list