SAS 2 - bit ordering for SNW-3 settings

Sheffield, Robert L robert.l.sheffield at intel.com
Fri Mar 23 14:07:57 PDT 2007


* From the T10 Reflector (t10 at t10.org), posted by:
* "Sheffield, Robert L" <robert.l.sheffield at intel.com>
*
Intel prefers option-(A).
Bob
-----Original Message-----
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of Elliott,
Robert (Server Storage)
Sent: Thursday, March 22, 2007 1:41 PM
To: T10 Reflector
Subject: RE: SAS 2 - bit ordering for SNW-3 settings
SCSI data structures are generally laid out as bytes:
    bit 7 6 5 4 3 2 1 0
byte
0	x x x x x x x x
1	x x x x x x x x
2	x x x x x x x x
3	x x x x x x x x
We could document the SNW-3 bits that way, provided we define the order
in
which they appear during SNW-3.
The START bit must be the first bit on the wire (or the protocol won't
work).
The PARITY bit should be the last bit on the wire (the protocol could
work
without that, but it's traditional to place parity at the end).
A) The data structure could be defined as:
  7	6	   5	4     3    2	 1    0
0 START TXSSCTYPE  Rsvd Rsvd  REQUESTEDLOGICALLINKRATE
1 G1NO	G1SSC	   G2NO G2SSC G3NO G3SSC Rsvd Rsvd
2 Reserved
3 Rsvd	Rsvd	   Rsvd Rsvd  Rsvd Rsvd  Rsvd PARITY
with the order on the wire as:
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1.7 1.6 ... 3.0
The MSB of REQUESTED_LOGICAL_LINK_RATE would be in bit 3
and go out on the wire first ("big end first").
B) Or the data structure could be defined as:
  7	 6    5     4	     3	   2	1	  0
0 REQUESTEDLOGICALLINKRATE   Rsvd  Rsvd TXSSCTYPE START 
1 Rsvd	 Rsvd G3SSC G3NO     G2SSC G2NO G1SSC	  G1NO
2 Reserved
3 PARITY Rsvd Rsvd  Rsvd     Rsvd  Rsvd Rsvd	  Rsvd
with the order on the wire as:
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.0 1.1 ... 3.7
The MSB of REQUESTED_LOGICAL_LINK_RATE would be in bit 7
and go out on the wire last ("little end first"). 
Since SAS is naturally big-endian, A) seems more natural.
--
Rob Elliott, elliott at hp.com
Hewlett-Packard Industry Standard Server Storage Advanced Technology
https://ecardfile.com/id/RobElliott
________________________________
	From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of
Sheffield, Robert L
	Sent: Thursday, March 22, 2007 1:17 PM
	To: Day, Brian; T10 Reflector
	Subject: RE: SAS 2 - bit ordering for SNW-3 settings
	Intel has assumed the opposite.
	Question - is the bit numbering in table-84 correct? In every
other
instance where bits in a field are transmitted across the wire, the
first
bit transmitted is the highest numbered bit in the field and is the
highest
order. Why is the start bit numbered "0" and not "31"? I think there's a
100% chance that breaking convention here will result in
non-interoperable
solutions.
	Bob
________________________________
	From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of
Day,
Brian
	Sent: Wednesday, March 21, 2007 1:39 PM
	To: T10 Reflector
	Subject: SAS 2 - bit ordering for SNW-3 settings
	Any opinions to the contrary?
________________________________
	From: Elliott, Robert (Server Storage) [mailto:Elliott at hp.com] 
	Sent: Wednesday, March 21, 2007 12:10 PM
	To: Day, Brian
	Cc: Stephen FINCH; Tim Symons; Amr Wassal; Alvin.Cox at seagate.com
	Subject: RE: bit ordering for SNW-3 settings
	Good question.
	Based on the bit layout proposed in 07-091 for the SMP
functions, I
think bit 4 should be the MSB and bit 7 should be the LSB.  That way, in
the
SMP functions, it will have its natural encoding.
	I suggest you post this Q&A to the T10 reflector to make sure
nobody
else has assumed the opposite.
	-- 
	Rob Elliott, elliott at hp.com 
	Hewlett-Packard Industry Standard Server Storage Advanced
Technology
	https://ecardfile.com/id/RobElliott 
________________________________
		From: Day, Brian [mailto:Brian.Day at lsi.com] 
		Sent: Wednesday, March 21, 2007 11:55 AM
		To: Elliott, Robert (Server Storage)
		Subject: bit ordering for SNW-3 settings
		Rob. 
		Can you clarify for me the bit ordering for the
REQUESTED
LOGICAL LINK RATE in the SNW-3 settings? 
		The example uses "9", which is the same bit flipped or
not. 
		Would be great to get a 1.5 example added to spec too
since
that would show correct bit positions. 
		Thanks! 
		__________ 
		Brian Day 
		LSI Logic 
		(719) 533-7468 
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