Calibration/Verification of Jitter Measuring Device

Chuck Hill cphill at
Tue Aug 21 07:04:54 PDT 2007

Attachment #1: <A HREF="r0708210_sas_jmd_calibration_v1.pdf">sas_jmd_calibration_v1.pdf</A>

Enclosed is a paper on calibration and verification of jitter measuring
devices.  It includes a procedure for setting a clock recovery circuit to
obtain reproducible results in the presence of low frequency phase noise.
Perhaps some of the material would be useful in your delibrations on the 6G
SAS specification.
Chuck Hill

More information about the T10 mailing list