sas1r03 Annex H.16
gil.romo at qlogic.com
Wed Feb 4 14:26:22 PST 2004
* From the T10 Reflector (t10 at t10.org), posted by:
* Gil Romo <gil.romo at qlogic.com>
I think there are a couple of new problems that could be cleaned up by the
1) It looks like Figure H.16 was copied and pasted from Figure H.15 and retained
the description that expander phys W and Z are part of an STP/SATA bridge.
However, H.16 is describing an OPEN address frame received by phy Z, a situation
that would not occur on a SATA link. This could be corrected by removing the
descriptions of expanders W and Z (ie, "STP target ..." or "SATA host port in an
STP/SATA bridge") in the figure.
2) When phy Z transitions to XL6 there will be an OPEN address frame received
argument, indicating that the incoming and outgoing OPEN address frames are to
be compared. As is evident in the absence of a backoff retry or backoff reverse
response, the OPEN address frame received by phy Z has a lower arbitration
priority. Therefore, I propose an alternate description of this figure, as
"Figure H.16 shows a phy whose link layer state machine receives a Transmit Open
indication while in the XL1 state. In this scenario, the OPEN address frame (B
to A) received by phy Z has a lower priority."
3) Wouldn't this figure fit nicer after H.7?
Any objections or comments?
Circuits & Integration
QLogic Corporation, Aliso Viejo, California
E-mail: gil.romo at qlogic.com
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