Revisiting the "starting paced transfers with no training pattern" requirement

Paul.M.Sweazey at Paul.M.Sweazey at
Wed Mar 20 17:50:10 PST 2002

* From the T10 Reflector (t10 at, posted by:
* Paul.M.Sweazey at

aka: P1 Phase Initialization Window

>> I would like everyone to review their implementations to see if 4
>> (i.e. cycles, 100 ns elapsed time at fast-160) of P1 is adequate to get
>> proper frequency lock.

Luckily, there is no need to wait for PLLs to lock. From a logic-design
perspective the P1 data-not-valid phase can be established during the very
first cycle of REQ/ACK. The only reason to wait is to allow the effect if
ISI to settle down. This effect is lessened by the fact that both REQ/ACK
and P1 are changing from an enduring negated state: the effect on BOTH
signals is to make the first transitions appear to occur later than they
were sent. The time shift is in the SAME direction for both signals. If
there is a problem sampling and establishing the data-not-valid phase
during the fourth P1 cycle (the 13th through 16th data transfer periods)
then we haven't much hope of capturing data later on.

Regarding wording, most all of it is ambiguous enough to guarantee frequent
misinterpretation unless the .e.g. wording is also considered and
reconciled with the preceeding words. In my opinion the most consistent
interpretation always leads to a data-not-valid training section that
endures for 16 data transfer periods. For FAST-160 that is 100 nS.

For SPI-5 FAST-320 it makes sense for the P1 phase initialization window to
remain at 16 data transfer periods. This is consistent with the
recommendations for training FAST-320 training patterns. On the other hand,
the P1 Phase Initialization Window isn't part of the "real" training, so
who cares if we make constant the number of data transfer periods or the
wall-clock duration.

The real problem is that the wording is too ambiguous, despite certain
defensive comments to the contrary at the most recent Parallel SCSI
meeting. The proof is that Bruce's implementation assumes 32 data transfer
periods rather than 16.

So what do we do? Do we declare those who may send a P1 Phase
Initialization Window of only 16 data transfer periods as illegal? Do we
declare those who need to receive a 32 period Window as broken? Do we set a
different rule for initiators than targets, hoping that no one is creating
an initiator that actually transmits the shorter window?

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