Paced mode: DT DATA IN followed by DT DATA OUT

Leshay, Bruce Bruce_Leshay at maxtor.com
Wed Jun 19 12:09:40 PDT 2002


* From the T10 Reflector (t10 at t10.org), posted by:
* "Leshay, Bruce" <Bruce_Leshay at Maxtor.com>
*
This was discussed at a T10 meeting quite some time ago, and 0 was the
agreed-upon number.  It was agreed that it was the initiator's problem if
they really were simultaneous or close to it (even a small number wouldn't
help because of skew).
My impression (since I don't design initiators) was that most initiators put
some sort of digital filter on phase changes anyway, to prevent a noise
glitch during a data transfer from causing a problem, and that this
filter/delay of phase changes simplified meeting the 0ns requirement.

				Bruce Leshay
				Maxtor Corporation

-----Original Message-----
From: Richard Moore [mailto:richard.moore at qlogic.com]
Sent: Tuesday, June 18, 2002 7:37 PM
To: T10 Reflector
Subject: Paced mode: DT DATA IN followed by DT DATA OUT


* From the T10 Reflector (t10 at t10.org), posted by:
* "Richard Moore" <richard.moore at qlogic.com>
*
In paced mode, when ending a DT DATA IN transfer, according to SPI-4
10.7.4.3.4, "the SCSI target port shall end pacing by waiting for all REQs
to be
responded to by ACKs then negate the REQ and P1 signals. After the SCSI
target port stops asserting and negating REQ it shall not assert REQ
again until the requirements in 10.12 are met."

What SPI-4 doesn't seem to say is how long the target must wait after the
last REQ negation before it changes any of C/D, I/O, or MSG. Is there
a minimum (other than zero)? If the target can change I/O simultaneously
with the negation of REQ, what keeps the initiator from seeing the last REQ
of a DT DATA OUT phase as the first REQ of the following DT DATA IN phase
(due to skew on the bus)?

 -- Richard Moore
    QLogic Corp.

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