What scsi phase should a target enter ...?

George Penokie gop at us.ibm.com
Mon Jun 17 07:11:09 PDT 2002


* From the T10 Reflector (t10 at t10.org), posted by:
* "George Penokie" <gop at us.ibm.com>
*

Luu,

No, the information in table 10 does not contain any sequencing
requirements. The PPR, SDTR, and WDTR sequencing rules are shown in figure
11 and then described in detail in section 4.12.7.

Bye for now,
George Penokie

Dept 2C6  114-2 N212
E-Mail:    gop at us.ibm.com
Internal:  553-5208
External: 507-253-5208   FAX: 507-253-2880




                                                                                                                                       
                      "Luu, Trung"                                                                                                     
                      <Trung_Luu at adapte        To:       "'George Penokie'" <gop at us.ibm.com>                                           
                      c.com>                   cc:       owner-t10 at t10.org, "'t10 at t10.org'" <t10 at t10.org>                              
                                               Subject:  RE: What scsi phase should a target enter ...?                                
                      06/14/02 09:08 PM                                                                                                
                                                                                                                                       
                                                                                                                                       



Hi George,

Thank you for your response.  However, I just want to confirm
on your response.  I look at section 4.12.4.6.2 of SPI-4 rev 10.
And the description that I found in this section that closes to
your response is in Table 10:

-----------------------------------------------------------------
Initial  Modified                             Bus phase following
IU_REQ   IU_REQ             Causes             MESSAGE phases
 value    value
------   --------   -----------------------   -------------------
   1        0       a) PPR negotiation ...;    BUS FREE phase
                    b) WDTR negotiation; or
                    c) SDTR negotiation
-----------------------------------------------------------------

So if I understand correctly, the 'WDTR negotiation' stated above
implies WDTR follows by SDTR.  Am I correct?

Thank you for your time,
-Trung Luu

-----Original Message-----
From: George Penokie [mailto:gop at us.ibm.com]
Sent: Friday, June 14, 2002 9:39 AM
To: Luu, Trung
Cc: owner-t10 at t10.org; 't10 at t10.org'
Subject: Re: What scsi phase should a target enter ...?



Luu,
As described in section 4.12.4.6.2 of SPI-4 rev 10; After the WDTR is the
SDTR then BUS FREE.

Bye for now,
George Penokie

Dept 2C6  114-2 N212
E-Mail:    gop at us.ibm.com
Internal:  553-5208
External: 507-253-5208   FAX: 507-253-2880






                      "Luu, Trung"

                      <Trung_Luu at adapte        To:       "'t10 at t10.org'"
<t10 at t10.org>
                      c.com>                   cc:

                      Sent by:                 Subject:  What scsi phase
should a target enter ...?
                      owner-t10 at t10.org





                      06/13/02 02:47 PM








* From the T10 Reflector (t10 at t10.org), posted by:
* "Luu, Trung" <Trung_Luu at adaptec.com>
*
Hello,

In section 10.5.2.3 of SPI-4 revision 9, the specs states that "... If the
first message received by the
SCSI target port during the MESSAGE OUT phase is not a TARGET RESET message
or PPR message
the SCSI target port shall change to a MESSAGE IN phase and issue a MESSAGE
REJECT message
then originate WDTR negotiation (see 4.12.7.5) with the TRANSFER WIDTH
EXPONENT field set to 00h."

In Section 4.12.7.5, figure 18, column 3. SCSI target port response with
WDTR OUT with legal values,
states that " ... The SCSI target port shall ... , abort all tasks to SCSI
initiator device if IU_REQ was
changed, and originate an SDTR IN."

And in Section 4.12.4.6.2, table 10 mentions the bus phases resulting from
IU_REQ changes.
If I'm understanding the specs correctly, it states that If an IU_REQ value
goes from 1 to 0 because of
WDTR negotiation, then the scsi bus phase following WDTR messages should be
BUS FREE phase.

My question is what scsi phase should a target enter right after a
completion of WDTR messages
if IU_REQ was changed i.e. from 1 to 0.?

Thank you in advance,
-Trung Luu
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