SCSI Reset

[Gerry.Houlder at seagate.com]

* From the T10 Reflector (t10 at t10.org), posted by:
* Gerry.Houlder at seagate.com
*

My answers are:

[1] yes.

[2] The "margin available" is not really specified in the standard, other
than the behaviors you noted in [1] (i.e., pulses shorter than 200 ns
should be ignored and longer pulses should result in target releasing all
signals by 400 ns). There is recommendation to initiators that a 25
microsec pulse width should be used for resets that are intentionally
issued. Since this is much longer than the 200-400 ns target response
requirement, we hope that real systems don't have pulses in the 200-300 ns
range that could be ambiguously interpreted by different target devices.



                                                                                                  
                    Krishnakumar                                                                  
                    Mattekkat                To:     t10 at t10.org                                  
                    <krishna_kumar_m@        cc:                                                  
                    yahoo.com>               Subject:     SCSI Reset                              
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                    12/19/2002 05:41                                                              
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* From the T10 Reflector (t10 at t10.org), posted by:
* Krishnakumar Mattekkat <krishna_kumar_m at yahoo.com>
*
Hello,

I have two questions on SCSI reset signal.

[1] If a SCSI device sees that the RST signal is
asserted for 300 ns (or any value greater than reset
delay period of 200 ns, should the device take it as a
valid reset and release the all the bus signals within
the bus clear delay  from transition to RST true?

[2] If the above is true (that is, a RST assertion of
more than reset delay is a valid reset), what is the
margin available for the SCSI device to detect a valid
RST vs rejecting it as a glitch (in terms of time)?

thanks for your time,

//kkumar//

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