krishna_kumar_m at yahoo.com
Thu Dec 19 03:41:45 PST 2002
* From the T10 Reflector (t10 at t10.org), posted by:
* Krishnakumar Mattekkat <krishna_kumar_m at yahoo.com>
I have two questions on SCSI reset signal.
 If a SCSI device sees that the RST signal is
asserted for 300 ns (or any value greater than reset
delay period of 200 ns, should the device take it as a
valid reset and release the all the bus signals within
the bus clear delay from transition to RST true?
 If the above is true (that is, a RST assertion of
more than reset delay is a valid reset), what is the
margin available for the SCSI device to detect a valid
RST vs rejecting it as a glitch (in terms of time)?
thanks for your time,
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at t10.org
More information about the T10