Question on QAS behavior wording

[Gerry.Houlder at seagate.com]

* From the T10 Reflector (t10 at t10.org), posted by:
* Gerry.Houlder at seagate.com
*
This is wording from SPI-4 rev. 7, section 10.4.4 describing QAS sequence:

The procedure for a SCSI target port with both information unit transfers and QAS enabled to indicate it
wants to release the bus after a DT DATA phase is as follows:

1) The SCSI target port shall change to a MESSAGE IN phase and issue a single QAS REQUEST
(55h) message (see 10.11.2) and waits for ACK to be true.

2) After detection of the ACK signal being false and if the SCSI initiator port did not create an
attention condition, the SCSI target port shall release all SCSI signals except the BSY, MSG, C/D,
I/O, and REQ signals. Then the SCSI target port shall negate the MSG, C/D, and I/O signals within
two system deskew delays. The SCSI target port shall wait two system deskew delays after
negating the C/D, I/O, and MSG signals before releasing the REQ signal.

3) If the SCSI initiator port did not create an attention condition then the SCSI initiator port shall
release all SCSI signals except ACK and ATN within two system deskew delays after detecting
MSG, C/D, and I/O signals false. The ACK and ATN signals shall follow the timing specified in
table 34.
4) If the SCSI initiator port creates an attention condition then the SCSI target port shall go to a
MESSAGE OUT phase, receive all the message bytes, and cause an unexpected bus free by
generating a BUS FREE phase (see 10.3).

5) If the SCSI target port detects the SEL signal being true, the SCSI target port shall release the
BSY, MSG, C/D, and I/O signals within one QAS release delay.

6) After waiting at least one QAS arbitration delay from releasing the SCSI signals in step (5), if there
are no SCSI ID bits true the SCSI target port shall transition to the BUS FREE phase.
7) After waiting at least one QAS arbitration delay from releasing the SCSI signals in step (5), if there
are any SCSI ID bits true the SCSI target port shall wait at least a second QAS arbitration delay. If
the SEL signal is not true by the end of the second QAS arbitration delay the SCSI target port shall
transition to the BUS FREE phase.

HERE ARE MY QUESTIONS:

(a) Step 6 seems to describe a case where QAS arbitration phase is entered
but there are no data bits on the bus. However step 6 seems to be
contingent on step (5) happening. Step (5) [which involves detecting SEL
signal being active] shouldn't happen if there are no bits on the bus.
Should this only require step (2) instead of step (5) as its prerequisite?

(b) Step 7 has the same issue in terms of requiring step (5) as a
prerequisite. It talks about data bits being true (active?) and SEL not
true, which suggests that step (5) [detection of SEL being true] couldn't
have happened. Should the reference to step (5) really be a reference to
step (2)?

(c) Step 7 has the target releasing BUSY (transitioning to bus free) even
though there are data bits on the bus if SEL has not occurred. Doesn't this
leave a risk that if the winning ID doesn't assert SEL soon enough (i.e.,
before this device releases BUSY) that a bus free transition will be seen
by some devices but perhaps not by others?

(d) There doesn't seem to be a step that allows the SCSI target port to
detect itself being the QAS winner (this should at least be possible if it
was the only device arbitrating) and assert SEL itself. Is this possibility
completely prohibited by the fairness rules?

Correct answers to questions (a) and (b) are required to tell if the
standard needs to be changed. The other questions are just my own wondering
into the details and may not have to be furhter addressed by the standard.

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