Transmit assertion/negation period

[Day, Brian]

* From the T10 Reflector (t10 at t10.org), posted by:
* "Day, Brian" <bday at lsil.com>
*
I've gone back and looked at the actual spreadsheet that was used to
generate that number (on the web site as 00-323r2.xls).

Here is what was used:

Transfer Period		+6.25
Period Tolerance		-0.06
Driver Asymetry		-0.0	
	(this was being pulled out of a row listed as "Double counting"...
that is why it is zero.  Normal value is 0.5) 
System noise @ launch	-0.25
Clock Jitter			-0.25


So clock jitter was being taken into account.  But can anyone explain why
the 0.5ns of driver asymetry shouldn't be included?  I don't see how it
would be double counted in this situation.

Brian Day
LSI Logic

> -----Original Message-----
> From:	Bill Galloway [SMTP:BillG at breatech.com]
> Sent:	Thursday, May 03, 2001 11:57 AM
> To:	T10 Reflector (E-mail)
> Subject:	Transmit assertion/negation period
> 
> * From the T10 Reflector (t10 at t10.org), posted by:
> * "Bill Galloway" <BillG at breatech.com>
> *
> Bill Petty brought up a concern about the Transmit assertion and negation
> period for Fast-160 in SPI-4. He was concerned that the times could not
> be met with legal slew-rates. Since the time is measured from zero
> crossing
> to zero crossing, I do not believe that slew rate matters.
> 
> I still think that PLL jitter may have been left out but not slew rate.
> 
> 
> Bill do you agree???????
> 
> 
> Bill Galloway
> BREA Technologies, Inc.
> P: (281) 530-3063
> F: (281) 988-0358
> BillG at breatech.com 
> *
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