Paced timing/protocol clarifications

Richard Moore richard.moore at qlogic.com
Fri Feb 16 11:03:19 PST 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* Richard Moore <richard.moore at qlogic.com>
*
Now that I think about it that wired-OR glitch is already there after
a reselect. I don't think it hurts anything because it gets filtered out.
That should still be the case during training.

Richard

-----Original Message-----
From: Richard Moore [mailto:richard.moore at qlogic.com]
Sent: Friday, February 16, 2001 10:55 AM
To: T10 at t10.org
Subject: RE: Paced timing/protocol clarifications


* From the T10 Reflector (t10 at t10.org), posted by:
* Richard Moore <richard.moore at qlogic.com>
*
* From the T10 Reflector (t10 at t10.org), posted by:
* "Day, Brian" <bday at lsil.com>
*
One thing to note is that the initiator could then hold onto the BSY line
until the SEL deasserts during training.  I don't see a problem with that...
just that BSY will be driven asserted by both the target and initiator until
the SEL deasserts.

Brian

...causing a wired-or glitch on BSY while SEL is false (looks like BUS FREE
if it lasts long enough).

Richard
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