Paced timing/protocol clarifications

Bill Galloway BillG at breatech.com
Mon Feb 12 14:02:54 PST 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* "Bill Galloway" <BillG at breatech.com>
*
Also on the SEL timing.  We still need a change in the spec.  Right now
section 10.8.4.2.2 requires the target to negate SEL after seeing BSY.

There is no reason for the target to negate SEL here if the target is
going to assert it for a training pattern.  The time from BSY to SEL is
a hold over from long ago.  The requirement should be that it negate
SEL 2 system deskew delays before the first REQ unless it wants training.


Bill Galloway
BREA Technologies, Inc.
P: (281) 530-3063
F: (281) 988-0358
BillG at breatech.com

-----Original Message-----
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org]On Behalf Of Day,
Brian
Sent: Monday, February 12, 2001 3:16 PM
To: 'George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com'; Day,
Brian
Cc: T10 at t10.org
Subject: RE: Paced timing/protocol clarifications


* From the T10 Reflector (t10 at t10.org), posted by:
* "Day, Brian" <bday at lsil.com>
*
George....

Thanks for the reply... however I'm still not clear on case 2 for stopping
the REQ prior to changing the phase lines.  The restriction you state makes
sense, but it really doesn't specify any minimum time.... just any time
greater than zero, which in effect could be "nearly" simultaneous.  As far
as the initiator is concerned then, it could still see REQ assertions after
the phase lines change given any amount of cable skew.   So my question is,
is that the intended behaviour of ending a DT DATA IN paced transfer?

Thanks...

Brian


> -----Original Message-----
> From:	George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com
> [SMTP:George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com]
> Sent:	Monday, February 12, 2001 1:54 PM
> To:	Day, Brian
> Cc:	T10 at t10.org
> Subject:	Re: Paced timing/protocol clarifications
>
> Brian,
> To answer your questions:
> 1-There is no time specified between the target's release of the SEL line
> and it's assertion of SEL for training in the case you describe.
> 2-No the target is not allowed to simultaneously negate the REQ/P1 and
> change the phase. This restriction is in section 10.8.1 as:
>
> "The target shall not transition into an information transfer phase unless
> the REQ and ACK signals are negated. The target shall not transition from
> an information transfer phase into another information transfer phase
> unless the REQ/ACK signals are negated."
>
> There is some further explanation in notes 33 and 34 that follow the above
> statement.
>
> As a result the REQ and ACK signals must both be negated before any phase
> change can be made.
>
> Bye for now,
> George Penokie
>
> Dept 2C6  114-2 N212
> E-Mail:    gpenokie at tivoli.com
> Internal:  553-5208
> External: 507-253-5208   FAX: 507-253-2880
>
>
> "Day, Brian" <bday at lsil.com>@t10.org on 02/08/2001 05:31:15 PM
>
> Sent by:  owner-t10 at t10.org
>
>
> To:   T10 at t10.org
> cc:
> Subject:  Paced timing/protocol clarifications
>
>
>
> * From the T10 Reflector (t10 at t10.org), posted by:
> * "Day, Brian" <bday at lsil.com>
> *
> I have a two questions about paced transfers.  Hopefully someone can point
> me to where in the Spi-4 draft these are covered (I couldn't find a direct
> answer).
>
> 1.  SEL behaviour when starting a training sequence after a reselection.
>      It's my understanding from section 10.7.2 that the target shall
> release the SEL line two system deskews after detecting the assertion of
> BSY
> from the initiator.  In section 10.8.4.2.2, it states that the target
> shall
> assert SEL two system deskews before asserting REQ.  How soon after
> releasing SEL from the reselection phase can a target reassert it to
> prepare
> for training?  Essentially, is there any minimum deassertion time between
> those two events?
>
>
> 2.  Ending pacing transfers from DT DATA IN
>      From section 10.8.4.3.4, the target negates the REQ and P1 lines
> once the offset has gone to zero.  Then it states the rules in 10.13 must
> be
> followed.  Is there any minimum time restriction on the target from
> negating
> the REQ/P1 to changing the phase lines?  If the target is allowed to
> simultaneously negate the REQ/P1 and change phase, the initiator may
> actually see a REQ in the new phase during that switch if the cable skews
> the REQ "slower" than the phase lines... which to the initiator would look
> like a violation of section 10.13.    I was expecting to find some
> requirement on the target for that, but didn't see one.
>
> Brian Day
> LSI Logic Corp.
>
>
>
>
>
> *
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