Paced timing/protocol clarifications

George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com
Mon Feb 12 12:53:44 PST 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* George_Penokie/Tivoli_Systems%TIVOLI_SYSTEMS at us.ibm.com
*
Brian,
To answer your questions:
1-There is no time specified between the target's release of the SEL line
and it's assertion of SEL for training in the case you describe.
2-No the target is not allowed to simultaneously negate the REQ/P1 and
change the phase. This restriction is in section 10.8.1 as:

"The target shall not transition into an information transfer phase unless
the REQ and ACK signals are negated. The target shall not transition from
an information transfer phase into another information transfer phase
unless the REQ/ACK signals are negated."

There is some further explanation in notes 33 and 34 that follow the above
statement.

As a result the REQ and ACK signals must both be negated before any phase
change can be made.

Bye for now,
George Penokie

Dept 2C6  114-2 N212
E-Mail:    gpenokie at tivoli.com
Internal:  553-5208
External: 507-253-5208   FAX: 507-253-2880


"Day, Brian" <bday at lsil.com>@t10.org on 02/08/2001 05:31:15 PM

Sent by:  owner-t10 at t10.org


To:   T10 at t10.org
cc:
Subject:  Paced timing/protocol clarifications



* From the T10 Reflector (t10 at t10.org), posted by:
* "Day, Brian" <bday at lsil.com>
*
I have a two questions about paced transfers.  Hopefully someone can point
me to where in the Spi-4 draft these are covered (I couldn't find a direct
answer).

1.  SEL behaviour when starting a training sequence after a reselection.
     It's my understanding from section 10.7.2 that the target shall
release the SEL line two system deskews after detecting the assertion of
BSY
|from the initiator.  In section 10.8.4.2.2, it states that the target shall
assert SEL two system deskews before asserting REQ.  How soon after
releasing SEL from the reselection phase can a target reassert it to
prepare
for training?  Essentially, is there any minimum deassertion time between
those two events?


2.  Ending pacing transfers from DT DATA IN
     From section 10.8.4.3.4, the target negates the REQ and P1 lines
once the offset has gone to zero.  Then it states the rules in 10.13 must
be
followed.  Is there any minimum time restriction on the target from
negating
the REQ/P1 to changing the phase lines?  If the target is allowed to
simultaneously negate the REQ/P1 and change phase, the initiator may
actually see a REQ in the new phase during that switch if the cable skews
the REQ "slower" than the phase lines... which to the initiator would look
like a violation of section 10.13.    I was expecting to find some
requirement on the target for that, but didn't see one.

Brian Day
LSI Logic Corp.





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