IU transfer exception handling

Mike Bratvold mbratvol at lsil.com
Wed Oct 11 15:04:59 PDT 2000


* From the T10 Reflector (t10 at t10.org), posted by:
* Mike Bratvold <mbratvol at lsil.com>
*
  After reading proposed SPI-4 R1 (00-378r0), I have questions about
exception handling during IU transfers.
  Three similar questions:

==============================================================================
1) What happens if ATN is asserted during the L_Q of an L_Q/Command IU pair,
   and there is an L_Q iuCRC Error during the L_Q?  Does the target receive 
   the asynchronous message or does the target go bus free?

Section 12.2 Attention Condition
g) If ATN is detected during an IU transfer, the target shall
enter MGS OUT phase at the completion ofthe current SPI IU.

10.8.3.3.4 DT DATA OUT IU transfer exception condition handling
If the target is receiving a SPI L_Q IU and the target detects
an iuCRC error (i.e. the nexus identification fails) the target
shall cause an unexpected bus free by generating a BUS FREE
phase.

I'm not sure whether the failure to establish an I_T_L_Q nexus
is the basis for the answer.
(from 14.2 IU transfer logic operations)
If there is a phase change to a MSG OUT or MSG IN phase then there
is no logic disconnect and the I_T_L_Q nexus remains in place. 

==============================================================================
2) What happens if ATN is asserted during the Command IU and 
   there is a iuCRC Error during the Command IU?  I assume that 
   the target can receive the asynchronous message prior to sending 
   status for the iuCRC error.

Section 12.2 Attention Condition
g) If ATN is detected during an IU transfer, the target shall
enter MGS OUT phase at the completion ofthe current SPI IU.

10.8.3.3.4 DT DATA OUT IU transfer exception condition handling
If the nexus has been fully identified (i.e. an I_T_L_Q nexus has been
established) and the target detects an iuCRC error in any SPI IU
it receives while in DT DATA OUT phase the target shall, before
receiving another SPI L_Q IU, switch to a DT DATA IN pahse and send
a SPI L_Q/SPI Status IU pair to the initiator with a CHECK CONDITION
status and ...

==============================================================================
3) What is the flow after ATN is asserted during the L_Q of 
   an L_Q/Command IU pair (no iuCRC error)?  It's clear that 
   the asynchronous message should be brought in by the target
   after receiving the L_Q IU. What should happen next?  It is
   not possible to go back and receive the Command IU, so
   I think that status should be sent.  I could not find where
   SPI-4 defines the action in this case.

Best Regards
Mike Bratvold

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
!  Mike Bratvold                                                  !
!  Logic Design Engineer                                          !
!  Storage ASICs and Coreware                                     !
!  LSI Logic Corporation                                          !
!                                                                 !
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!                                        FAX (970) 206-5244       !
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