SPI-4 P1 Line

[Gene_Milligan at notes.seagate.com]

* From the T10 Reflector (t10 at t10.org), posted by:
* Gene_Milligan at notes.seagate.com
*

Vince wrote:

<<If the smallest increment of data or not data is 4 bytes (two edges of
the
clock) the P1 signal will not transistion if the data source sends 4 bytes
of data followed by two clock edges of no data and repeats this process. Is
there something in the definition to not allow this to happen?>>

     Richard Moore's proposal which I have included in 99-295r4 has "The
minimum data invalid time is four data transfer periods. This ensures a
maximum run length of three cycles for P1. The data invalid state shall
last an even number of transfer periods."

     Note that it is four transfer periods not four bytes. This prevents DC
for those that think P1 needs to have more margin than data bits. I think
the error detection works even if P1 were to be the same as the data bits
(i.e., DC allowed).

Gene


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