SPI-4 P1 Line

[Bruce Leshay]

* From the T10 Reflector (t10 at t10.org), posted by:
* Bruce Leshay <Bruce.Leshay at quantum.com>
*
Vince,

	The original proposal on this from Richard Moore stated that when
the phase of P1 changes to indicate "data invalid", it is required to remain
in that state for at least two clock edges (8 bytes worth of data).  This
prevents the scenario you are describing, which I believe occurs if you send
"data valid", "data invalid", "data valid", "data invalid", on alternating
rising clock edges, since each change of data state requires a phase change.
	At the time, there was some discussion of whether this was really
necessary - what was wrong with the line just going DC for awhile if someone
really toggled between data valid and data invalid every other clock edge?
Its such an unusual situation, its not likely to persist for very long - and
if it does the logic should work correctly in any case.  However, my memory
is that the sense of the committee was to adopt Richard's proposal.  We
should probably briefly revisit this issue this week, decide, and then Mark
can put it into his document that captures the whole clocking and
calibration stuff for SPI-4 in "standards format".

					Bruce

-----Original Message-----
From: Bastiani, Vince [mailto:bastiani at corp.adaptec.com]
Sent: Friday, April 14, 2000 1:52 PM
To: 't10 at t10.org'
Subject: SPI-4 P1 Line


* From the T10 Reflector (t10 at t10.org), posted by:
* "Bastiani, Vince" <bastiani at corp.adaptec.com>
*
The current proposals for SPI-4 utilize the P1 line to indicate data valid
or invalid using a phase change approach to switch between data valid and
invalid. 
If the smallest increment of data or not data is 4 bytes (two edges of the
clock) the P1 signal will not transistion if the data source sends 4 bytes
of data followed by two clock edges of no data and repeats this process. Is
there something in the definition to not allow this to happen?
Thanks,
Vince Bastiani

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