SPI-4 P1 Line

[Richard Moore]

* From the T10 Reflector (t10 at t10.org), posted by:
* Richard Moore <r_moore at qlc.com>
*
Vince,

In 99-324 we requested a minimum of four clock edges for data
not valid. If this provision is accepted, then the run length
of P1 will be limited.

 -- Richard Moore
    QLogic Corp.

>-----Original Message-----
>From: Bastiani, Vince [mailto:bastiani at corp.adaptec.com]
>Sent: Friday, April 14, 2000 10:52 AM
>To: 't10 at t10.org'
>Subject: SPI-4 P1 Line
>
>
>* From the T10 Reflector (t10 at t10.org), posted by:
>* "Bastiani, Vince" <bastiani at corp.adaptec.com>
>*
>The current proposals for SPI-4 utilize the P1 line to 
>indicate data valid
>or invalid using a phase change approach to switch between 
>data valid and
>invalid. 
>If the smallest increment of data or not data is 4 bytes (two 
>edges of the
>clock) the P1 signal will not transistion if the data source 
>sends 4 bytes
>of data followed by two clock edges of no data and repeats 
>this process. Is
>there something in the definition to not allow this to happen?
>Thanks,
>Vince Bastiani
>
>*
>* For T10 Reflector information, send a message with
>* 'info t10' (no quotes) in the message body to majordomo at t10.org
>
*
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at t10.org