SPI-4 P1 Line

[Bastiani, Vince]

* From the T10 Reflector (t10 at t10.org), posted by:
* "Bastiani, Vince" <bastiani at corp.adaptec.com>
*
The current proposals for SPI-4 utilize the P1 line to indicate data valid
or invalid using a phase change approach to switch between data valid and
invalid. 
If the smallest increment of data or not data is 4 bytes (two edges of the
clock) the P1 signal will not transistion if the data source sends 4 bytes
of data followed by two clock edges of no data and repeats this process. Is
there something in the definition to not allow this to happen?
Thanks,
Vince Bastiani

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