Suggested simulations for LVD timing meeting

Walter Bridgewater wally at
Fri May 21 16:05:39 PDT 1999

* From the T10 Reflector (t10 at, posted by:
* wally at (Walter Bridgewater)

You aren't quite getting the idea of what worst case (skew) is for
a receiver.

You don't want to start at 175mV and goto to -175mV.

What you really need to do is start at 10mV and goto -175mV,
and then start at -10mV and goto +175mV, and do this with about
1ps risetime and do this both for a positive edge and a negative
edge.  (Slower risetimes may reduce the skew.)

>From all 4 delays you get, you want to subtract the smallest number
|from the largest number, provided they are different edges.
The difference is telling you how much input reciever skew you are
getting. For numbers like 10/175mV, for sure, you have more than
1.25ns skew.

You want to increase the 10mV number, in steps, until 175mV.  At some
point, on the way to 175mV, you may see that increasing the level any
more, just isn't getting you very much reduction in skew.

You have to keep in mind, increasing the drive level to get more
input level is going to run up your power bill.  So, you have to
decide, at what input level do you want to be, to get the best, or
most effective input skew reduction, and keep you output power 
dissipation as low as possible.



> From relliott at Fri May 21 15:25:48 1999
> Return-Path: <t10-owner at Symbios.COM>
> From: relliott at (Robert Elliott)
> Subject: Suggested simulations for LVD timing meeting
> To: t10 at Symbios.COM
> Date: Fri, 21 May 1999 17:15:52 -0500 (CDT)
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> * From the T10 Reflector (t10 at, posted by:
> * relliott at (Robert Elliott)
> *
> To: all the pad designers planning to attend the LVD timing meeting 
> next week in Colorado Springs
> To explore the issues, you may want to run SPICE (or equivalent) on 
> your SCSI LVD input receiver and measure the input delays for 
> these cases.
> 1. The best case signal meeting the rules.  
> Start level at +175 mV then change almost instantly to -175 mV.  
> This should cause the fastest switching possible in the receiver.  
> Repeat for a positive edge transition.
> 2. Worst case signals meeting the rules.  
> Total time from 0mV to -175 mV is 3 ns.  
> 2a.  Start level at +175 mV, then drop to 60 mV instantly, then 
> stay level until 3 ns and drop to -175 mV.
> 2b.  Start level at +175 mV, then drop to 60 mV (taking almost 
> 3 ns from 0 mV to 60 mV), then drop to -175 mV instantly.
> Repeat for positive edge transitions. 
> 3.  General characterization.
> Start the signal at +175 mV.  Switch to these voltage levels:
>     +30 mV
>     0 mV
>     -30 mV
>     -60 mV
>     -90 mV
>     -120 mV
>     -150 mV
>     -175 mV
> with these edge rates:
>     -50 mV/ns
>     -100    
>     -200    
>     -300    
>     -400    
>     -500    
>     -1000
> and measure how long the receiver takes to switch.
> Repeat for positive edge transitions from -175 mV.
> Consider the results from 1) and 2).  What if the clock signal has
> with the best case waveform and the data signal has the worst case 
> waveform.  Assume the worst combination of rising/falling edges
> (in DT, they all matter).  Do the receiver input delay differences 
> eat up all of the 1.25 ns ASIC setup and hold time?  When the 
> ASIC designers do timing analysis, what numbers are they using for 
> LVD pad skews?  If using SPICE, are they running best/worst case 
> waveforms or assuming some similarity?
> Other things to consider:
> When "shall detect" is 60 mV, there's probably too much variation
> in receiver delay for an ASIC to work correctly if the system
> delivers legal but different signals.  It's fair to require more
> similarity of signal edges from the system than the current spec
> requires, but how can you express that? 
> If the  "shall detect" level was specified at 175 mV and "may detect" 
> was specified at 0 mV, the ASICs would probably all work fine no matter
> how the signals look getting to 175 mV.  However, this puts extra burden 
> on the system board/interconnect.   
> Is there some level (e.g. 115 mV) where the pad variation is
> well within the 1.25 ns setup time, so no additional signal
> correlation requirements on the interconnect need to be created?
> -- 
> Rob Elliott   UNIX mailto:relliott at    
> Houston, TX     PC mailto:Robert.Elliott at
> *
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