Reason for the CRC_A extra timing

Richard Moore r_moore at
Thu May 6 10:13:10 PDT 1999

* From the T10 Reflector (t10 at, posted by:
* Richard Moore <r_moore at>
At the SPI-3 Working Group meeting this week, Rob Elliott presented
99-185r0, which proposes
removing the extra setup time from the CRC_A signal for parallel CRC
transfers in DT mode.
The justification for keeping the extra setup time is as follows:
1. Although the data lines are potentially subject to the same maximum ISI
as CRC_A, the CRC_A
is involved in the protection of the data. If the data misses its setup time
at the receiver due to excess
ISI, then we want the CRC to accurately detect resulting errors. If CRC_A
should miss its setup at the
receiver, then the scheme becomes less reliable. We want our protection
scheme to be more robust
than the data path we are trying to protect.
2. If detection of CRC_A true at the initiator occurs too late on a pad word
transfer, then the initiator
will think there are no pad bytes and:
    a. For DT Data In transfers, the initiator will see 4 data bytes where
it should have seen two
    data bytes and two pad bytes. Since the last two bytes are included in
the CRC calculation at
    both ends, the check of the CRC immediately following will not detect an
error. But, the pad bytes
    will be transferred to the host memory.
    b. For DT Data Out transfers, the initiator will send 4 data bytes where
it should have sent
    two data and two pad bytes. The target will throw away the last two data
bytes, thinking they
    are the pad bytes it requested. Again, the CRC check will not detect
this error because the
    two discarded bytes are included in the CRC calculation at both ends.
3. If detection of CRC_A true at the receiver occurs too late on an unpadded
CRC transfer, then
the initiator will see a shortened CRC_A signal (spanning only one clock
edge). This is an error
condition that the initiator has to be prepared to handle anyway, but
changing the spec means the
likelihood of this error may increase.
4. Note that although most of the concern is about the CRC_A false-to-true
transition, it is possible
for the target to stop a transfer with CRC_A asserted for a long time.
Although less likely, this event
would make CRC_A vulnerable to ISI on the true-to-false transition. This
creates another set of
failure modes that can be detected by the initiator; consequently the extra
setup time is a good thing
to have on both transitions of CRC_A.
As you can see, I do not think it would be wise to remove the extra CRC_A
setup time requirement.
In addition, I do not think the justification for the proposed change has
been made clear; there is only
a vague reference to expander flexibility.
 -- Richard Moore
    QLogic Corp.
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