QAS release glitch management

Richard Moore r_moore at qlc.com
Thu May 6 09:54:18 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Richard Moore <r_moore at qlc.com>
*
At the SPI-3 Working Group meeting this week, it was suggested that QAS
might be vulnerable to
release glitches and that Table 23 does not cover QAS. This is a small hole
that can be easily fixed.
 
Consider each signal group from Table 23, bearing in mind that an LVD SCSI
release glitch occurs
when releasing a signal from the actively negated state:
 
1. BSY, SEL, RST -- These are wired-OR (hence, passively negated) signals;
consequently you
do not have release glitches on these lines. This holds during QAS as well.
2. ACK, ATN -- These signals are negated by the initiator at the end of the
Message In phase for
the QAS message. Currently a release timing for these signals during QAS is
not specified. These
signals should be released only after detecting the change out of Message In
phase after the QAS
message has been ACKed. Similarly, the target should begin ignoring these
signals no later than
a Bus Settle Delay after the phase change after the QAS message is
completed. The condition is
no different than for non-QAS except that the reference point is the phase
change from Message In,
rather than the release of BSY.
3. REQ -- Delays of 2.5 * Bus Settle Delay for the target and 1.5 * Bus
Settle Delay for the initiator,
both relative to BSY release, are specified for non-QAS. The large delays
are required because BSY
is passively negated and hence may need a round-trip bus delay to guarantee
detection. QAS does
not rely on BSY but on the actively negated phase control lines, so a
smaller delay (such as one or
two deskew delays) is sufficient. However, I believe the initiator should
not expect any more messages
after QAS and so could begin ignoring REQ as soon as it negates ACK for the
QAS message byte,
and if this is done then the target could actually release REQ at any time
after negating it.
4. C/D, I/O, MSG -- The release timing for these signals during QAS is
already defined in 11.1.2.2.1 (e).
This happens after SEL is true, at which time no devices are examining these
signals (all initiators
are disconnected, and the one that is selected (or being reselected) hasn't
completed the QAS selection
phase).
5. DATA BUS (SELECTION and RESELECTION) -- This line holds for QAS as well.
6. DATA BUS (information transfers) -- This line holds for QAS as well.
 
The changes in (2) and (3) are minor technical changes. (1), (5), and (6)
require no changes (other
than to say that they DO apply to QAS, which was the case in the previous
rev of SPI-3). (4) does not
seem (to me) to require a technical change but maybe a note should be added
to say what is going on.
I will prepare a proposal to incorporate these changes into Table 23 and the
applicable paragraphs of
the QAS section.
 
 -- Richard Moore
    QLogic Corp.
 
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