CRC Protection for Non-Data transfer phases

Chandru Sippy c_sippy at
Mon Mar 1 12:23:29 PST 1999

* From the T10 Reflector (t10 at, posted by:
* Chandru Sippy <c_sippy at>
Hi Jim!

I read the CRC proposal (T10/99-119 r0b) you put together. It is a very
interesting idea and quite intriguing. However, my main concerns are the

*	You propose a new CRC algorithm that would require additional
*	A run is predefined. Hence if implemented by hardware, it would not
be easy to change
*	Not backwards compatible with an 8-bit bus

I would like to offer a suggestion that accomplishes what you propose but
has very little impact on any existing or new hardware implementations. The
suggestion is as follows:

*	Use the same CRC algorithm as the DT transfer phases (no new CRC
*	Let the target determine the run described by your proposal and
request for CRC as done by the current DT implementation. Future
implementations can be changed easily since implementation in hardware is
not mandated. The CRC overhead of 4 bytes is a penalty but it is backward
compatible with an 8-bit bus, if the SPI-3 specification is amended.
*	Lastly, the CRC overhead introduced above can be reduced by allowing
non-data transfer phases to use the upper SCSI bus bits 15 - 8 to transfer
command, message, and status information as well by exchanging PPR messages.
This actually speeds up the non-info transfer to some extent. A typical CDB
of 10 bytes followed by ID, Tag (2), and PPR msg (8) for a total of 21 bytes
can be reduced to 11 + 2 = 13 REQ/ACK handshakes instead of the current 21
REQ/ACK handshakes needed. This would require some steering logic for these
phases in hardware but the impact should be small since it already exists
for DT transfer phases. The committee will have plenty of ideas of how to
deal with extra unwanted ODD byte outlined by the above example. At this
point, I haven't given it much thought.

I believe the above suggestions accomplish the same ends as described by
your new CRC proposal but with much less impact on hardware for any new or
existing SCSI chip designs.

Let me know what you think?


Chandru M. Sippy.
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