Arbitration and Data Out bus phase similarities?

Dale Smith dale at data-transit.com
Wed Aug 11 08:59:41 PDT 1999


* From the T10 Reflector (t10 at t10.org), posted by:
* Dale Smith <dale at data-transit.com>
*


Regarding a Data Out being mistaken for an Arbitration Phase...
The short answer on this is that it can't happen as long as
a device follows the rules for arbitration since a device must
detect Bus Free before arbitrating. To Arbitrate without 
detecting the Bus Free could certainly result in the mess you 
have described.

Dale

***************************************************************


At 07:45 AM 8/11/99 -0600, Art Rodgers wrote:
>Just a quick question.  I just noticed that the Arbitration and Data Out
>phase look the same (looking at BSY being asserted and SEL, C/D, I/O,
>ATN, MSG being deasserted).  If the situation occurred where we were in
>the middle of the Data Out phase (synchronous) and a target (call it
>targ1) has REQ'd up to the max offset and is having to waiting an amount
>of time for the ACK's.  In this time frame a second target (targ2)
>decides that it is going to try and reselect the initiator.  If it looks
>at the bus at this point could it confuse the Data Out phase for an
>arbitration phase and drive BSY and it's ID onto the bus.  Additionally,
>if this can occur ,then if the Initiator starts to respond with the
>ACK's and driving data onto the bus at the same time then there could be
>an unknown on the lower 8 bits of the data bus.  I'm not even sure how
>often (if at all) this situation could present itself, but what would
>the proper way to handle this be?  Thanks.
>
>Art Rodgers
>
>Attachment Converted: "S:\EudoraDale\Attach\art.rodgers.vcf"
>
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