Fast-80 Items

Gregory D Kapraun Gregory.D.Kapraun at
Thu Sep 3 20:34:04 PDT 1998

* From the T10 (formerly SCSI) Reflector (t10 at, posted by:
* Gregory D Kapraun <Gregory.D.Kapraun at>

I would like to second your observations and caution with the one good
backplane and one bad one example.  We have seen examples where only 2
Ultra2 SCSI devices would operate at Fast-40 operation until most of the
design was modified to adhere to SPI-2 minimum spacings and stubs. 
Although this was not a backplane, it showed that 'normal' systems that
have not been thoroughly engineered have a low probability of working. 
This is probably why there is not a multitude of LVD systems shipping yet.
 We have also seen that impedance mismatches between backplane and
interconnect(mother) boards as well as the cable running from the host to
the box can dramatically impact the quality of the signals observed on the
bus.  This particular backplane behaved as if it was not terminated until
issues again with spacing and impedance mismatches were corrected.  We
have a long way to go in getting good LVD backplanes operating at Fast-40
speeds before Fast-80 will ever work.  I would second your call to have
some sort of backplane Annex.  Another concern observed is that although
it is good Marketing to remain backwards compatible, it does not appear
that trying to design a backplane to run both SE and LVD mode is very
easy.  The reflections generated due to taking a middle of the road
impedance spec. to fit within the design space for either SE or LVD have
caused some of these systems to not operate when fully or partially
populated.  I'm not sure this has done any favors for the systems
developers and may push some away from SCSI implementations as the speeds
continue to increase.

Gregory Kapraun
Western Digital

From: 	Duncan Penman[SMTP:Duncan.Penman at]
Sent: 	Thursday, September 03, 1998 7:46 PM
To: 	't10 at'
Subject: 	Fast-80 Items

* From the T10 (formerly SCSI) Reflector (t10 at, posted by:
* Duncan Penman <Duncan.Penman at>
We have no new timing studies to present for the September T10 meeting.
There are a couple of points to follow up on from the July meeting that I
would like to document here, as I won't be able to make St. Petersburg

1. In T10/98-199r0, which showed setup and hold times for different data
sequences, some people noted that there appears to be some low pass
filtering of the data bit waveform that doesn't appear in the REQ
I.E., DB5 is made up of smooth curves while REQ shows some sharp
Unfortunately I still haven't been able to duplicate the configuration
the waveforms were captured.  The LVD backplane I used was a loaner that
been returned to the vendor that supplied it.  No luck so far in getting

2. In general, the signals on this same LVD backplane looked quite good,
even 11+ meters away from the signal source.  The question was raised
whether we had looked at any other backplanes.  In September the answer
no.  However, last week we got one day with a second LVD backplane and the
contrast was extreme.  While the first backplane would run 6 devices error
free at Fast-40 speed on a 12m bus, this one failed at Fast-40 speed with
single device on a 2m cable.  At .5m it seemed solid, and that is the
configuration in which it ships.  The initial look at waveforms showed
poor signal quality on the bit causing the most bus parity errors.  I
to have a few more days with this backplane in late September to see
the problem is due to poor design or an out-of-spec component such as an
onboard terminator chip.  So we now have two examples, one good and one

The reason for mentioning this second case now is to raise a warning flag
that backplanes, with or without attached motherboards, are likely to be
Achilles heel of LVD at higher speeds.  While requirements for cable
configurations are well documented in SPI-2 and SPI-3, requirements or
guidelines for backplane configurations are pretty mysterious.  Also
probably pretty tough to develop, but most LVD drives will be going into
disk arrays where backplanes are the norm.  An informative annex, at
dealing with backplane considerations for SCSI buses seems like a
addition to SPI-3.  I'll be happy to contribute to the effort but don't
qualified to be the primary author.  Comments?

Duncan Penman
Quantum Corp
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