Revised Draft Agenda -- SPI-2/SPI-3 Working Group Meeting

John Lohmeyer lohmeyer at
Wed Mar 4 11:41:15 PST 1998

* From the T10 (formerly SCSI) Reflector (t10 at, posted by:
* John Lohmeyer <lohmeyer at>
REVISED Draft Agenda -- SPI-2/SPI-3 Working Group Meeting
March 16, 1998 -- San Diego, CA

1.  Opening Remarks
2.  Approval of Agenda
3.  Attendance and Membership
4.  SPI-3 Topics
  4.1   Staged Contact Resistance [AMP]
  4.2   Load Compensation (97-281) [Novak]
  4.3   Universal Backplane Annex (98-101) [Wallace]
  4.4   Bias Reduction Proposal (97-214) [Bridgewater]
  4.5   Dual Clocking Proposal (97-208) [Bastiani]
  4.6   Test results on dual clock signals (98-113r0) [Bastiani]
  4.7   Need for error detection on dual-edge clocks (98-114r0) [Gintz]
  4.8   Packetized Protocol review (97-230r5) [Penokie/Williams]
  4.9   QAS review 97-199r7 [Moore]
  4.10    CRC proposal for SPI-3 [Penokie]
5.  SPI-2 Topics
  5.1   0.5 pF balance capacitance for LVD SCSI (97-236) [Aloisi/Kapraun]
  5.2   Removal of overlapped commands checking in SPI-2 [Williams]
  5.3   Terminator Power voltage level [Wallace]
  5.4   SPI-2 Proposed letter ballot response review (98-108r1) [Penokie]
6.  Meeting Schedule
7.  Adjournment

I've corrected the author and version in item 4.9.

In the previous version of the draft agenda I misstated the Adaptec 
position.  They do plan to present some additional data on their SPI-3 
topics.  Apparently, their test chip just arrived, so there may not 
be much data available on item 4.6.

John Lohmeyer                  Email: lohmeyer at
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4420 ArrowsWest Dr.              Fax: +1-719-533-7036
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