Voltage mode driver penalty

[RMoore at corp.adaptec.com]

* From the SCSI Reflector, posted by:
* RMoore at corp.adaptec.com
*
Form: Memo
Text: (53 lines follow)
To SPI-2 meeting attendees:

At Monday's meeting I stated that the driver DC test circuit would impose a 
penalty on voltage mode drivers; i.e., the driver would have to be stronger 
than required by worst-case bus conditions just to comply with the test. 
Here is my analysis.

We established minimum Va and Vn (magnitudes) of 270 mV and 260 mV for the 
driver in the test circuit. If Ia and In are the Norton equivalent driver 
strengths for assertion and negation, and Rs is the driver source impedance, 
then

	|Va| = (Ia - 2.1 mA) * (54.5 || Rs) >= 270 mV
	|Vn| = (In + 2.1 mA) * (54.5 || Rs) >= 260 mV

The minimum Ia and In values to satisfy these relationships as functions of 
Rs can be obtained easily. The minimum Ia and In values to satisfy the bus 
requirements are also functions of Rs. The two sets of functions (test 
conditions and bus conditions) do not track each other perfectly, however. 
Here is a table listing several Rs values and the associated minimum Ia and 
In requirements for both the test circuit and actual worst-case bus 
conditions:

	Rs		Ia min (test)	In min (test)	Ia min (bus)		In min (bus)	Penalty

	5		61.1			54.7			37.3			33.0		64%
	10		34.1			28.7			21.7			17.4		57%
	20		20.6			15.7			14.0			 9.6			47%
	40		13.8			 9.2				10.1			 5.8			37%
	100		 9.8				 5.3				 7.7				 3.4			26%
	250		 8.1				 3.7				 6.8				 2.5			19%
	1M		 7.1				 2.7				 6.2				 1.9			14%

The penalty column represents the percentage excess of assertion current 
required by the test circuit over that required by the bus. As Rs decreases, 
the penalty increases. A similar trend applies to the negation current 
penalty.

Requiring voltage mode drivers to pass the same test as current mode drivers 
forces voltage mode designs to use substantially higher power than needed. 
It would be better to define a separate test for voltage mode drivers, 
applicable to drivers with source impedances less than or equal to around 40 
ohms. At present I don't have a proposal in mind for this but I would like 
to hear suggestions. Two possibilities may exist: (1) Same test circuit, 
different test conditions, plus a qualifying test to determine if the 
voltage mode or current mode conditions are applicable; (2) a separate test 
circuit (different resistances?) that favors voltage mode drivers (i.e., 
having a positive slope for penalty vs. Rs). In the latter approach, drivers 
would only have to pass one of the two tests to be compliant, so designers 
could choose a test circuit that is more applicable to their design.

	Richard Moore
	Adaptec Irvine Technology Center
Use Proportional Font: true
Attachment Count: 0
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