LVD SCSI driver strength

[RMoore at corp.adaptec.com]

* From the SCSI Reflector, posted by:
* RMoore at corp.adaptec.com
*
Form: Memo
Text: (101 lines follow)
Since we ran out of time at the SPI-2 meeting on Monday, I was unable to 
present the material I had on LVD SCSI minimum drive strength requirements. 
I plan to show this in San Jose next month but in the meantime here's a 
summary.

Kevin Gingerich has already presented a numerical analysis. I took an 
algebraic approach. I think the results of the two methods are in reasonably 
close but not perfect agreement. On the other hand I don't think my analysis 
is completely redundant, since the resulting inequalities provide some 
useful insights.

I used the following constraints: VA >= 130 mV, VN <= -130 mV (DC voltage 
levels); V+ >= 150 mV, V- <= -150 mV (AC voltage levels, 1st transition); ZL 
ranging from 85 to 135 ohms (I used a purely distributed cable load model); 
VB ranging from 100 mV to 130 mV and RT ranging from 100 to 115 ohms 
(terminator bias and resistance); and magnitude of IL <= 20 uA per load with 
up to 16 loads (leakage current). For convenience, I defined the directions 
of IA and IN so that they are always positive.

For assertion I derived several inequalities, but the one relating to 
incident wave voltage was the dominant requirement:

	IA >= 7.02 mA + .35 * IN		to generate incident wave voltage >= 150 mV

For negation the incident wave inequality is also the dominant one:

	IN >= 1.61 mA + .35 * IA		to generate incident wave voltage <= -150 mV

If these two inequalities are graphed we get a wedge-shaped region of 
operation, with the point corresponding to IN = 5 mA and IA = 9 mA just 
inside the tip of the wedge.

A few caveats: My model may be overly pessimistic, compared to the 
spreadsheet model, in how I treated the leakage current (both models are 
simplistic in assuming a constant current for the leakage). I also neglected 
source impedance. Last, since I modeled only a distributed load impedance, 
reflections from loads do not appear in this analysis.

I conclude with the following observations:

(1) If I have analyzed the output voltage test in the annex correctly, a 
driver will pass when IA is between 9.7 and 15.0 mA, IN is between 4.9 and 
15.8 mA, and IA - IN lies between -0.9 mA and 7.5 mA. This defines the 
intersection of a rectangle with a diagonal band. I did not define any upper 
boundaries but if we use the same upper boundaries while replacing the 
rectangular region with the new wedge region, and also adopt some 
symmetry/asymmetry limits (not necessarily those given in the annex), then 
the resulting region falls almost entirely within the region allowed by the 
test circuit. However, there are areas that would be allowed by the test 
circuit that lie outside the wedge. If we check the extreme points of these 
"wings" (4.9/12.4 and 10.6/9.7) against the spreadsheet model, they do pass, 
but I'm not convinced that there aren't cable configurations which might 
fail for these points. Furthermore, the test conditions in the annex would 
exclude the tip of the wedge (including the aforementioned 5/9 point). If 
you plug 5 mA and 9 mA into the spreadsheet, it passes, except for the 
release-from-negation glitch (which needs to be handled by some other means) 
and for the assertion to passive transition (which is covered by a SPI-2 
rule that says a signal must be negated before being released).

I think that while the test circuit itself is valid, we may need to change 
the test limits so that the limits of the measured assertion and negation 
voltages are not constants but functions of each other. The minimum negation 
drive should also be lowered to allow the 5/9 point to be included. If I 
have time I hope to have some proposed limits for this table by the next 
meeting.

(2) The shape and position of the wedge strongly favors asymmetrical 
drivers, in case we haven't seen enough reasons to go asymmetric. Symmetric 
drivers enter the wedge at around 11 mA, and if we adopt 15 mA as the upper 
limit, how easy is it for silicon designers to control the drive strength 
tightly enough to keep within these limits? The lower asymmetric limit of (5 
mA, 9 mA) will give more latitude to the designers and also lower the power 
requirements.

(3) The dominant requirements arise from the need to produce a sufficient 
incident wave for the case of minimum loaded cable impedance and maximum 
termination resistance. For drivers that meet this requirement, it turns out 
that the incident wave for the opposite case of high loaded cable impedance 
and low termination resistance is large enough to compensate for the 
reflections from the terminators.

(4) Item 3 suggests that we can ease the minimum drive requirements by 
lowering the maximum RT. A range of 100 to 105 ohms for RT would be nice, in 
my opinion. This will reduce the inequalities above to:

	IA >= 6.98 mA + .24 * IN
	IN >= 1.57 mA + .24 * IA

which lowers the minimum asymmetric drive to around (4 mA, 8 mA) and the 
minimum symmetric drive to around 9.2 mA.

(5) Finally, one question: For a released signal, the magnitude of the 
negated signal falls to that of the loaded termination bias, which can be 
around 81.6 mV. Does this steady state passive negation level provide enough 
noise margin, or do we need a higher termination bias voltage?

Any comments will be appreciated.

	Richard Moore
	Adaptec Irvine Technology Center

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