# LVD SCSI Bus Termination I-V Plots

Siegfried Schmalz Siegfried.Schmalz at dalsemi.com
Tue Feb 20 12:00:37 PST 1996

```* From the SCSI Reflector, posted by:
* Siegfried.Schmalz at dalsemi.com (Siegfried Schmalz)
*

I have two questions regarding the LVD SCSI bus termintation
as described in SPI-2 rev 04 (January 23, 1996).

1. NAMING CONVENTIONS: It would be customary to define
positive current as flowing from the positive node of a
voltage source, through the source, to the negative node
of that voltage source. Also, one would expect that
Vdiff = (V+) - (V-).  Using these conventions, however, I
am unable to duplicate Figure 3 (page 15).
There are, therefore, two possibilites:

a) I am mistaken in my understanding of the naming
conventions that are to be used for this spec.
b) The plot of Figure 3 is to be drawn as a
mirror image (about the Y axis) from where it
is presently drawn.

The following HSPICE deck illustrates my question.
----------------------------------------------------------
*** One of the proposed termination schemes ***
vtop top 0 dc 1.5
vbot bot 0 dc 1.0
rtop top minusig 240
rmid minusig plusig 130
rbot plusig bot  240
************************************************

vdc dcoff 0 dc 1.25v
vsw plusig dcoff dc 0
esw minusig dcoff plusig dcoff -1.0

.dc vsw -0.5 0.5 0.1

.probe dc
+      vdif=par('v(plusig)-v(minusig)')
+      i1=par('i(vsw)')

.print dc
+      par('v(plusig)-v(minusig)')
+      par('i(vsw)')

.end
----------------------------------------------------------
When this HSPICE deck is run, a mirror image of Figure 3

2. X INTERCEPT RANGE OF FIGURE 5:  The range along the Voltage
axis of Figure 5 where current is 0 is specified to be
from 100mV to 130mV). However, if one takes the
test circuit of Figure 4 and sweeps the applied voltage,
one sees that the common mode current is 0 when the voltage
being swept is at 1.25V; this is what one would intuitively
expect for a termination centered at 1.25V. Hence, the
question is:

a) Are the values for V1 and V2 correct in Figure 5?

The following HSPICE deck illustrates my question.
----------------------------------------------------------
*** One of the proposed termination schemes ***
vtop top 0 dc 1.5
vbot bot 0 dc 1.0
rtop top minusig 240
rmid minusig plusig 130
rbot plusig bot  240
************************************************

rshort plusig minusig .00001
vswp plusig 0 dc 0
.dc vswp .7 1.8 0.1

.print dc
+      par('i(vswp)')

.end
----------------------------------------------------------
When this HSPICE deck is run, a mirror image of Figure 5

Siegfried Schmalz

Dallas Semiconductor
schmalz at dalsemi.com
(214) 450-3764

```