Stephen_Finch/SSI1.SSI1 at notes-gw.tus.ssi1.com
Tue May 23 03:40:20 PDT 1995
In regard to Walter Bridgewater's comment:
The C/D, I/O and MSG signals must be valid 400 ns (a bus settle delay) before
can be asserted. These signals are, therefore, stable long before the transfer
and do not change during the transfer, so no change need be made to the
of these signals unless we are planning to change bus settle delay.
The BSY, ATN, SEL and RST lines do not change during a transfer, so their
need not change either.
I agree that REQ, ACK, REQQ, ACKQ, data and parity need to be changed.
/To: scsi @ wichitaks.ncr.com @ TSMTP
/From: wally @ eng.adaptec.com (Walter Bridgewater x2371) @ TSMTP
/Date: 05/22/95 12:20:59 PM
/Subject: RE: SPI-2/Fast-40 pins
/I agree that at least ack, req, data & parity have to be differential
/for the reasons Tak suggest.
/If the other 7 signals are single ended,
/Then their slew rates should be slowed down proportional to any
/length increase beyond 3 meters.
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