Server SPI Background and Working Group Agenda Material
ham at subsys.ENET.dec.com
ham at subsys.ENET.dec.com
Mon Mar 20 06:36:22 PST 1995
This memo outlines the situation with the new "High Performance
Server SPI" that was created in Newport Beach at the SPI futures
It has been well established that FAST 20 single ended SCSI has
some limits that are significant. For FAST 40 SCSI there have been no
reports of any tests with single ended configurations (due to dearth of
single ended silicon that will run at FAST 40 speeds). FAST 40 single
ended may be limited to point to point applications or very short
busses with very few devices.
On the other hand, it has been well established that
differential SCSI does not suffer from the configuration limits of
single ended and working FAST 40 differential transmissions were
demonstrated over a year ago using off the shelf components.
The limitations with differential have traditionally been in the
cost and in the skew hits implied by the use of a multichip interface.
Barriers to single chip differential, which is the key to acheiving low
cost and low skew, have been formidable. The two most often quoted
barriers are power dissipation and high common mode levels demanded by
the present differential SCSI specifications.
At the Newport Beach meeting two things happened that may
dramatically change the barriers to single chip differential
implementations: (1) the introduction of AC coupled bus termination and
(2) limitations on the common mode level implied by the use of the
single ended DIFF SENSE line.
A scheme for terminating the differential SCSI bus with a
combination of line matching AC coupling and relatively high impedance
DC bias (to set the state when no device is driving) was proposed by
Unitrode. AC termination schemes have been used for years in the
Com business and have the property that the power consumption is confined
almost exclusively to the lines and times when signal transitions are
actually occurring. The present differential termination is DC coupled
and consumes power ALL the time when the bus is driven by a driver chip.
AC termination produces varying degrees of reductions in power (depending
on the activity level on the bus).
As far as the common mode level is concerned the present
implementation of the DIFF SENSE line limits the practical level to
something like 2 volts. This is much lower than the design values
required by the present differential SCSI specfication.
Taking both the new termination scheme and the lower common mode
levels into account may be enough to open the door to low cost single
chip differential SCSI. Part of the activity needed over the next few
weeks is a thorough analysis of the real power savings attainable by the
AC termination (especially for FAST 20 and FAST 40) and of the impact of
lower common mode levels.
Present differential SCSI has by far the largest common mode
levels of any storage bus of current interest. This alone should be
enough to seriously consider reducing the level.
It was pointed out by QLogic that once the differential
interface is integrated into a single chip that it may be possible to
also have that same chip offer a single ended option. Since the
pinouts are different for single ended and differential this may not be
trivial. The chip could sense the type of termination being used on the
bus segment and automatically set its interface accordingly. This would
produce the possibility of a single chip interface for all SCSI (narrow,
wide, single ended, differential). It would require more pins than a
single ended interface alone but otherwise may be acheivable. This
concept also needs careful scrutiny over the next few weeks.
One of the really attractive features of the AC termination is
its compatibility with present differential interfaces. By simply
changing the differential terminators to the new AC style, a bus that
can mix old and new devices is instantly produced. The voltage levels
do not need to be changed from the present levels.
Another area that may prove very fruitful for differential power
reduction is the use of 3.3 V supply voltage for the driver chips.
Again, more careful analysis is needed.
Clearly, since all drivers and receivers are in the same chip
the line to line skew will be very significantly reduced over a
multichip implementation. This invites FAST 40 or faster thoughts.
Also the risks of system integration and EMI may be greatly reduced over
serial techniques because the basic frequency content is almost the same
as today's SCSI (another real benefit of parallel). Note that wide FAST
40 is 80 MBytes/s per bus. With a 4 port VHDCI implementation this is
320 MBytes/s from a single PC slot.
There is much analysis and examination of application
assumptions needed before declaring that the holy grail of SCSI
(physical parts) is within reach. On the other hand, these new
approaches may offer enough to enable the single chip SCSI interface
that would bring all the benefits of differential at the single ended
The Agenda for the April Server SPI working group will attempt
to cover the items mentioned above (See J. McGrath SCSI reflector memo
More information about the T10