Fast-20 single-ended SCSI test circuit

Kevin Gingerich S=Kevin_Gingerich%S=Gingerich%G=Kevin%TI at
Mon Mar 6 05:41:00 PST 1995

  To  SCSI Reflector   X400
>From  Kevin Gingerich  GING
Subj  Fast-20 single-ended SCSI test circuit
I have been meaning to respond to the concerns raised about the switching
test circuit for a Fast-20 driver so, here goes.
The purpose of the test circuit in figure 1 of Fast-20 rev 3 is to verify
the driver switching performance and not the output voltage levels. (The
signal levels on the bus are to be assured through the driver dc output
specifications and testing.) The switching specifications and test circuit
are to limit radiated emissions and measure bus signal timing.
Reduction of radiated emissions is accomplished by limiting the high
frequency energy in the driver output signal through a maximum voltage slew
rate requirement. The driver output voltage slew rates of the positive-going
and negative-going transitions are a function of
a) the driver output transistors' turn-on and turn-off times,
b) the load impedance, and
c) initial circuit conditions.
The objective then is to define these variables in a compliance test that
will assure the maximum voltage slew rate requirement is met under
conditions to be encountered in actual use. Obviously the output
transistors' turn-on and turn-off times are the parameters to be measured,
leaving b) and c) for specification.
What is the load impedance? I would hope that no one believes the Fast-20
SCSI bus is not a distributed parameter circuit that takes on the electrical
characteristics of a transmission line. The lossless transmission line model
is a resistor and, as with any model, there are simplifying assumptions
made. A SCSI bus is obviously not infinite in length nor lossless as assumed
in the resistor model. However, the bus length compared to the shortest
wavelength of the signals makes the model sufficiently accurate to warrant
its application. Therefore, the load impedance for a driver is the parallel
combination of the two resistors representing either two lines or the
termination resistor and a line. Since the load is resistive, it affects the
signal voltage levels and not the ac response.
What are the initial circuit conditions? When a signal line is asserted for
at least three round-trip delay times of the line, the voltage is less than
0.5 V and there is approximately 48 mA flowing through the lines (resistor).
When the bus is negated for the same period, the voltage is between 2.5 V
and 3.7 V and there is approximately 0 mA flowing through the lines
(resistor). The 2.5 V source and 47 ohm resistor in figure 1 and a compliant
active-negation driver provides the correct initial circuit conditions.
The final considerations for the output voltage slew rate test are the effects
of the instrumentation and signal levels on the measurement. Using a 10x
scope probe with a tip capacitance of 10 pF to 15 pF will increase the 10% to
90% rise or fall time measurement 40% to 60% respectively. CL is not part of
the bus circuit model. There can be no lumped capacitance representing the bus
since we have already defined the load as a transmission line modeled by a
Since the magnitude of the resistive load is not necessarily that of a real
Fast-20 bus, the output levels may not be compatible with the requirement as
currently written. Changing the voltage range to apply the slew rate
restriction from fixed voltages to percentages of the steady-state output
levels will address this inconsistency.
The conclusion is that the circuit of figure 1 with a CL of 10 pF to 15 pF
is sufficient to verify compliance of the Fast-20 SCSI single-ended driver
output voltage slew rate requirement.
Signal timing is a function of the same variables above plus the additional
variables of multiple driver circuit delays and electrical paths. Since
these are the parameters to be measured, the analysis for the voltage slew
rate measurement applies here as well. The same test circuit can be used for
signal timing measurements.

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