Fast-20 Active Negation Drivers
JLOHMEYE at cosmpdaero.ftcollinsco.ncr.com
Tue Jan 31 14:05:00 PST 1995
+ Date: January 31, 1995
+ From: John Lohmeyer (john.lohmeyer at hmpd.com)
+ To: Tak Asami (asami at dt.wdc.com)
+ cc: scsi at wichitaks.ncr.com
>There are two concerns:
>- Do we want to keep 2.0V @ Ioh=7mA requirement?
> If a driver is powerful enough to supply sufficient current in
> then the requirement is almost automatically satisfied, but is this DC
> spec still required? Perhaps not, since the value of active negation is
> really in the rise transit. So John's picture (if it is drawn
> with finer resolution graphics) is totally agreeable.
If I understand your concern, you would prefer the diagonal load line to end
on the right side at 2.0V, 7mA. I assume it would then go vertical down to
2.0V, 0mA, as shown below:
30 mA | |xxxxxxxxxxxxxxxxxx
22 mA + |xxxxxxxxxxxxxxxxxx
20 mA |\___ +---+xxxxxxxxxxxxxx
10 mA |xxxxxxxxxxxxxxxxxxxxx\____ |xxxxxxxxxxxxxx
7 mA |xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| +--------+xxxxx
0 mA +---------------+---------------+---------------+---+-------+-----
0V 1V 2V 3V 3.24V 3.7V
Figure 1 -- Active Negation Current vs. Voltage
I do not have any problem with making this change and will revise my
committee proposal accordingly (of course, with better resolution graphics).
>- The load model on (current) Figure 1 is totally inadequate to be used
> for slew rate and AC transition characteristics design / validation.
> I prefer to use (unfortunately) a transmission line model like shown
> below as Figure 2.
By Figure 1, I assume you mean the test circuit that has been in Fast-20 for
| \ | 47 Ohm +/- 5%
| / | _|_
|/ ------- C | + |
------- L | | 2.5 V
(Isn't ASCII art fun?!?)
I agree that it is not a particularly good representation of our actual
load, but if we were to change the test circuit, then we may have to
re-address at least the slew rate specs and perhaps others. I was trying to
keep the lid on Pandora's Box by not changing too much in my proposal.
Your circuit is an excellent circuit to use to simulate a real load (and
your TTY art is pretty good, too :-), but I would rather have a simpler
circuit in the standard. This circuit will probably have to be built by at
least some of our customers for chip qualification. If it is too
complicated, it will be difficult to achieve consistent test results.
By the way, one thing that is not clear is where do you intend the 2.5 V be
connected to the terminators? I assume you intend each terminator to be:
110 Ohm +/- 5%
| + |
| | 2.5 V
In any case, I'd rather not bundle the test circuit issue with the minimum
negation current issue. If you wish to pursue the test circuit issue, I'd
prefer that you generate a separate proposal; if it is accepted, I can help
with creating the drawing for the working draft.
John Lohmeyer E-Mail: john.lohmeyer at hmpd.com
NCR Microelectronics Voice: 719-573-3362
1635 Aeroplaza Dr. Fax: 719-573-3037
Colo Spgs, CO 80916 SCSI BBS: 719-574-0424 300--14400 baud
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