Significant question on unfound and possibly missing words
Bob.Snively at eng.sun.com
Thu Jan 5 20:33:46 PST 1995
In X3.131-1994 (SCSI-2) section 6.1.10 places signal restrictions
between phases in the following manner:
6.1.10 Signal restrictions between phases
When the SCSI bus is between two information transfer phases, the
following restrictions shall apply to the SCSI bus signals:
a) The BSY, SEL, REQ, REQB, ACK and ACKB signals shall not change.
b) The C/D, I/O, MSG, and DATA BUS signals may change. When switching
the DATA BUS direction from out (initiator driving) to in (target
driving), the target shall delay driving the DATA BUS by at least
a data release delay plus a bus settle delay after asserting the I/O
signal and the initiator shall release the DATA BUS no later than
a data release delay after the transition of the I/O signal to true.
When switching the DATA BUS direction from in (target driving) to
out (initiator driving), the target shall release the DATA BUS no
later than a deskew delay after negating the I/O signal.
c) The ATN and RST signals may change as defined under the descriptions
for the attention condition (see 6.2.1) and reset condition (see
Note that this places an 800 nsec requirement between the change
|from command phase with I/O not asserted to the first signaling
on the Data Bus for the status phase with I/O asserted.
I do not find comparable wording in SIP or SPI. Our experience
indicates that this timing is quite important, especially
on differential buses, and should be followed. However, I have
not yet been able to locate this information in SCSI-3, so I would greatly
appreciate some expert indicating to me where
in SIP or SPI this information is contained.
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