Minutes: P1285/X3T10 Co-located Meeting 7/19/94

Martin Freeman martin at savant.prpa.philips.com
Mon Sep 26 09:31:08 PDT 1994

To:		Distribution
From:		Martin Freeman
Date:		September 14, 1994

Subject:	Minutes of IEEE P1285/X3T10 Co-located Meeting on 7/19/94

The P1285 Scalable Storage Interface working group, led by Martin
Freeman of Philips Research, met in conjuntion with X3T10 on Tuesday,
July 19, 1994 during the X3T10 meeting week in Manchester, New
Hampshire. The meeting started at 5:30 PM with the following

     Ruben Yomtovian    Hitachi Computer          
     Paul Boulay        Hitachi Computer          
     Robert Liu         Fujitsu Computer
     Roger Cummings     StorageTek
     Bob Snively        Sun
     Ed Cady            Harbor/Berg
     Martin Freeman     Philips Research      

Proposed Agenda

The following agenda was proposed by Martin Freeman and was approved by
the group at the beginning of the meeting:

	* Introductions
	* Current Status
	* Beta Level
	* Gamma Level
  	* Meeting Schedule

As is customary, everyone briefly introduced himself to the group.  A
sign-up sheet was circulated for attendance. Please contact Martin
Freeman (415)354-0329 for copies of the sign-up sheet. 

Current Status

Martin Freeman said that there had been recent collaboration with IEEE
P1596 SCI with respect to aspects of the P1285 gamma level. He
mentioned that there was interest in the SCI community in using P1285
along with PCI. One attendee indicated that he was present as a result
of this interest.

Beta Level

Martin presented an overview of the beta level as several attendees
needed to leave early for another meeting, the meeting day having
several parallel sessions.

Gamma Level

Most of the meeting was concerned with discussing the gamma level and
how it operated. During this discussion, several issues were touched

One issue that came up involved the use of spindle sync in disk array
configurations. It was pointed out that a disk array could be
implemented without spindle sync, instead using zero latency read
operations along with a DMA controller to map and transfer the data to
the right places in main memory.

Issues involving addressabilty and error reporting were also

The P1285 gamma level as currently specified provides for a main memory
resident linked list of device commands associated with each device. A
device is provided with a pointer to this list by writing a special
device register. The device then sequences through the list executing
commands. These commands call for the moving of data between the
device's media address space and the main memory address space. In this
respect a device is identified by its Command and Status Register space
which contains a pointer to the device command list.  Thus, each device
has its own address space.

It was pointed out that a uniform address space across devices was
desirable, with separate device address spaces viewed and accessed as
their combination. The interesting aspect of storage interface
approaches is at what level of the system the uniform address space is

Error handling can affect operation latency. Two approaches were
discussed --- let the system decide how the error is to be handled or
let the device decide. The former approach calls for the device to
report errors to the next higher level authority for disposition. This
authority provides the policy while the device provides the mechanism.
For instance, in the case of a disk drive with an error that cannot be
corrected by ECC, the next higher level would have to command the drive
to heal the problem.

The latter approach seeks to isolate the system from this by the device
always performing the healing process itself.  This hiding of error
processing from the system affects the predictability of the latency of
device operations. However, a question was raised as to the feasibility
of having predictable latencies, especially if external influences like
device placement near power supplies affects device operation

This discussion led into one on request re-ordering and where it should
be done --- at the device level or at a higher level. Re-ordering
requests at a higher level reduces the work of the device. However, one
view was expressed that the higher system levels could not know
accurately where data really was on the device because of logical block
address mapping. Consequently, the device would be the best place to do
the request reordering. The effect of the request reordering policy on
shared systems was then discussed.

The discussion ended at 9:15 PM.

P1285 Meeting Schedule

	October    6    Apple Computer, 1 Infinite Loop, Cupertino, CA
	November   3    Quantum Corp., 500 McCarthy Blvd, Milpitas, CA
        November   ?    P1596 Co-located Meeting, Santa Clara University

Unless otherwise notified, these meetings will take place between
2:00-5:00 PM.

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