SPI Tolerance

Bill=Galloway%HW=Stor%Sys=Hou at bangate.compaq.com Bill=Galloway%HW=Stor%Sys=Hou at bangate.compaq.com
Fri May 27 15:52:01 PDT 1994


I have recently come across a potential problem in SPI.  Compaq has a
system that negotiates for a period of 100ns but transmits with a
period of 99.776ns.  This system has been working for over a year but
we recently found a drive that would not work because of this.

There is no tolerance specified for the negotiation period in SPI.

This particular design uses a PLL with a frequency of 40.09Mhz.  If
the design had used a 40.00 Mhz crystal the tolerance would have been
much better but not perfect.  How good is good enough????  I am not
trying to allow RC circuits for oscillators, but I am trying to get
initiator and target manufacturers to agree on what is interoperable.

I would like to propose a change to SPI to specify a tolerance.

I am looking for some early feedback on the feasibility of this and
on what the tolerance should be.  My initial proposal would be a
tolerance of +/- 0.25 %.


Bill Galloway                           P.O. Box 692000
Compaq Computer Corp.                   MS 090504
(713) 374-6732                          Houston, TX 77269-2000

billg at bangate.compaq.com

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