Date: Nov 28, 1991 X3T9.2/176 Rev 1
To: X3T9.2 Committee (SCSI)
From: George Penokie (IBM)
Lee Cleveland
Subject: SCSI Data Phase LRC Proposal
Problem
As SCSI buses are loaded down with more devices 8 - 16 - 32 and
fast SCSI setup and hold times used, the SCSI bus needs to have more
error detection available. This detection needs to be able to detect
double clocking of Request and Acknowledge and even parity.
Questions
1-Which phases should the LRC apply?
-Data phase only
-Command phase and Data phase
-Only Data phases which read or write data to media
2-What should be the mechanism for enabling the LRC?
-Control bit in the CDB
-Mode Select page
-Message negotiation (e.g. like wide and fast)
3-What should the period at which the LRC is applied?
-Over a fixed number of bytes (e.g. every 512 bytes)
-Over the entire data transfer phase
-Over a variable number of bytes
4-If the number of bytes is variable how is the value determined?
-Mode Select page
-Message negotiation (e.g. like wide and fast)
5-Over what range should the LRC cover?
Initiator Target
Buffer -- Drivers ============ Drivers -- Buffer -- Media
-Between the Initiator Driver and the Target Driver
-Between the Initiator Driver and the Target Buffer
-Between the Initiator Driver and the Target Media
-Between the Initiator Buffer and the Target Driver
-Between the Initiator Buffer and the Target Buffer
-Between the Initiator Buffer and the Target Media
6-What type of error detecting scheme should be used?
-LRC
-CRC
-Reed Solomon
Solution using LRC
Implement a Longitudinal Redundancy Check (LRC) scheme were the data is
segmented into blocks that are checked for longitudinal parity. This
scheme would detect error caused by double clocking and even parity.
Description
A seed is agreed to by the initiator and target. The seed is 1 byte
for an 8 bit bus, 2 bytes for a a 16 bit bus, or 4 bytes for
a 32 bit bus. The 2 byte and 4 byte values are generated by
duplicating the seed 2 and 4 times.
The seed and data is XORed together at the initiator and the target as
the data is sent across the bus. The last data byte transferred for
the I/O process is the result of the XOR. This byte is compared to the
XOR generated by the receiving device, if they match the data
transferred was good.
An example of a 3 byte data transfer with LRC follows:
S E N D RECEIVE
------------------- --------------- ---
B B B S B B B R S
S Y Y Y S Y Y Y
E T T T L E T T T L L
E E E E R E E E E R R
D 1 2 3 C D 1 2 3 C C
------------------------- -----------------------------
7 XOR 7 XOR 7 XOR 7 = 7p 7 XOR 7 XOR 7 XOR 7 = 7 7p
6 XOR 6 XOR 6 XOR 6 = 6p 6 XOR 6 XOR 6 XOR 6 = 6 6p
5 XOR 5 XOR 5 XOR 5 = 5p 5 XOR 5 XOR 5 XOR 5 = 5 5p
4 XOR 4 XOR 4 XOR 4 = 4p 4 XOR 4 XOR 4 XOR 4 = 4 4p
3 XOR 3 XOR 3 XOR 3 = 3p 3 XOR 3 XOR 3 XOR 3 = 3 3p
2 XOR 2 XOR 2 XOR 2 = 2p 2 XOR 2 XOR 2 XOR 2 = 2 2p
1 XOR 1 XOR 1 XOR 1 = 1p 1 XOR 1 XOR 1 XOR 1 = 1 1p
0 XOR 0 XOR 0 XOR 0 = 0p 0 XOR 0 XOR 0 XOR 0 = 0 0p
P XOR P XOR P XOR P = Pp P XOR P XOR P XOR P = P Pp
------------------------- ------------------------------
S LRC = The sending devices generated LRC
R LRC = The receiving devices generated LRC
If S LRC is not equal to R LRC then an error occurred in the data
transfer.
Implementation:
A bit in the Standard Inquiry Data called LRC.
A Longitudinal Redundancy Check (LRC) bit of one indicates that the
device supports Longitudinal Redundancy Checking for this logical unit.
A value of zero indicates the device does not support Longitudinal
Redundancy checking for this logical unit.
A bit called ACTLRC and an 8 bit field called LRCSEED in the Control
Mode Page.
An Activate Longitudinal Redundancy Checking (ACTLRC) bit of one
specifies that the target shall use Longitudinal Redundancy Checking
for all data phase transfers. An ACTLRC bit of zero specifies that the
target shall not use Longitudinal Redundancy Checking.
The Longitudinal Redundancy Checking Seed (LRCSEED) field is only valid
if the ACTLRC bit is one. The target shall use this field as the seed
for all transfers of data which use Longitudinal Redundancy Checking.