Proposal posted: SAS-3 addition of POWER DISABLE

Felton, Mickey mickey.felton at emc.com
Fri Aug 17 07:44:00 PDT 2012


Formatted message: <a href="http://www.t10.org/cgi-bin/ac.pl?t=r&f=r1208173_f.htm">HTML-formatted message</a>

Can you provide a reason?
I believe the reasoning from Alvin on 3 was because 1 and 2 were always
connected together on “other systems”..
From: T. C. McNally [mailto:tc.mcnally at newisys.com]
Sent: Friday, August 17, 2012 8:51 AM
To: Besmer, Brad
Cc: Felton, Mickey; Alvin Cox; T10 Reflector
Subject: Re: Proposal posted: SAS-3 addition of POWER DISABLE
All,
Is the pin choice for POWER DISABLE negotiable?  I would ask for this
function to be on P1.
Thanks,
T. C. Mc Nally
System Engineer
719-884-8733
On Thu, Aug 16, 2012 at 4:16 PM, Besmer, Brad
<Brad.Besmer at lsi.com> wrote:
Alvin,
Few discussion items:
1 - There is no associated support in SPL-2 for this (ie. Identify /
Discover). How does the attached entity know if the target device supports
this behavior or not?
2 –What happens to the link-state when the POWER DISABLE signal is
asserted?
3 – How does attached device know if the device has been hot-swapped with a
different device?
4 – What other system-level impacts does this have?
Brad
From: owner-t10 at t10.org<mailto:owner-t10 at t10.org>
[mailto:owner-t10 at t10.org<mailto:owner-t10 at t10.org>] On Behalf Of Felton,
Mickey
Sent: Thursday, August 16, 2012 3:39 PM
To: Alvin Cox; T10 Reflector
Subject: RE: Proposal posted: SAS-3 addition of POWER DISABLE
Alvin-
EMC agrees with the principal behind this proposal, but a few questions:
How long after stable 12V / 5V is the circuitry ready? Could it be asserted
while power is ramping up?
Does the input signal on the drive have any special edge or level
requirements?
Thanks!
-Mick
From: owner-t10 at t10.org<mailto:owner-t10 at t10.org> [mailto:owner-t10 at t10.org]
On Behalf Of Alvin Cox
Sent: Thursday, August 16, 2012 12:33 PM
To: T10 Reflector
Subject: Proposal posted: SAS-3 addition of POWER DISABLE
This proposal changes the functions of P1, P2, and P3 from 3.3V. The signal
assignment of these pins have been changed by other standards that intermate
with SAS connectors. Please review this proposal. The proposal may be
downloaded at:
  http://www.t10.org/cgi-bin/ac.pl?t=d&f=12-363r0.pdf
This proposal was introduced on the 8/16/12 SAS PHY call and will be the
first discussion item on the 8/23/12 SAS PHY call.
Abstract
This proposal documents the changes associated with the addition of POWER
DISABLE to SAS-3. This function provides a means for the SAS target device
with a SAS Drive plug connector or SAS MultiLink Drive plug connector to
remove D.C. power (+5V and +12V) from the drive circuitry when the power
disable signal is driven high by the system. The POWER DISABLE signal is
specified on P3. If POWER DISABLE is not supported, P3 shall be not
connected. P1 and P2 are shorted together to provide the same connection as
on SAS drives compliant with versions of the SAS standard previous to SAS-3,
and to be consistent with the recommended implementation specified by SATA
since P1 and P2 have been retired and P3 may implement DEVSLP. The functional
polarity of POWER DISABLE is consistent with DEVSLP if the DEVSLP function is
enabled.
 Extensive research was done prior to drafting this proposal with respect to
system implementation on P1, P2, and P3. No instances were found where
systems provided 3.3V power to these pins. Maintaining the connection of P1
to P2 provided the widest support of legacy implementations that used the
pins for functionality not specified by the SAS standard.
--
Alvin Cox
Seagate Technology, LLC
Cell 405-206-4809<tel:405-206-4809>
Office 405-392-3738<tel:405-392-3738>
E-Mail	alvin.cox at seagate.com
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