Chained Q elements

Neil Wanamaker Neil_Wanamaker at pmc-sierra.com
Mon Mar 21 14:51:57 PDT 2011


* From the T10 Reflector (t10 at t10.org), posted by:
* Neil Wanamaker <Neil_Wanamaker at pmc-sierra.com>
*
Joe,
The CHAINING COUNT field in the IU is not meaningful to the queuing layer -
it is supplied for the benefit of the SOP layer. The incrementation of the
producer index tells the recipient how much to DMA.
A DMA controller that supports S/G could do this in one operation; a DMA
controller that does not would require two DMAs. 
In neither case are (blocking) reads across PCIe from the controller CPU
required. 
Neil
-----Original Message-----
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of Joe Breher
Sent: Monday, March 21, 2011 4:05 PM
To: T10 Reflector
Subject: PTI: Chained Q elements
* From the T10 Reflector (t10 at t10.org), posted by:
* Joe Breher <joe at lingua-data.com>
*
In regards to the PTI chaining mechanism, there are a couple other things
that occurred to me after we left the topic. If we are chaining elements, it
seems to me that there would still be a requirement for multiple DMAs in
order to transfer an 'operation' between controller and host memory.
- We don't know that there would be chained elements until we DMA the first
element, and check it's CHAINING COUNT.
- with a circular Q, there is a discontinuity in memory addresses where the Q
wraps. Will a typical DMA controller wrap appropriately without further
setup?
Am I missing something?
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