Block Reads on 2-Wire miniSAS HD Management Interface

McGrath, James jmcgrath at email.cinch.com
Mon Oct 12 20:25:10 PDT 2009


* From the T10 Reflector (t10 at t10.org), posted by:
* "McGrath, James" <jmcgrath at email.cinch.com>
*
Mick, anything T10 decides for QSFP must be compatible with the current
memory map described in SFF8436. There are areas of the memory map that
could be modified without effecting the current registers. But we need
to make sure anything we do for SAS does not create an incompatibility
problem for all the QSFP+ cables in data centers today. 
Jim McGrath
Cinch Connectors
1700 Finley Road
Lombard, IL 60148
office: 630-693-2040
mobile: 630-244-3872
-----Original Message-----
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of
Felton_Mickey at emc.com
Sent: Monday, October 12, 2009 3:37 PM
To: Barry.Olawsky at hp.com; t10 at t10.org
Subject: RE: Block Reads on 2-Wire miniSAS HD Management Interface
* From the T10 Reflector (t10 at t10.org), posted by:
* <Felton_Mickey at emc.com>
*
Barry/T10:
Another question I had was on the I2C address for the common interface,
will it be the same as QSFP today?
Are there any benefits to some other strategy/address?
Thanks!
-Mick
-----Original Message-----
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of Olawsky,
Barry
Sent: Friday, July 31, 2009 2:58 PM
To: t10 at t10.org
Subject: Block Reads on 2-Wire miniSAS HD Management Interface
* From the T10 Reflector (t10 at t10.org), posted by:
* "Olawsky, Barry" <Barry.Olawsky at hp.com>
*
In response to the "block read" question posed during the PHY meeting on
7/30/2009, virtually all 2-wire serial EEPROM devices currently
available support sequential reads (block reads). 
Adding the requirement for sequential read support may not appear
necessary for discrete EEPROM implementations but is probably prudent
for micro-controller implementations. For the latter, existing 2-wire
interface cores lacking support for sequential reads may end up being
used due to cost or availability of an existing core design. Explicitly
defining sequential read and write operations should prevent that from
occurring.
I recommend including this requirement in the timing diagram section of
the SFF QSFP document. Timing of the serial data line state determines
if the access is sequential or single byte.
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