SNW-3 SATA port selector confusion

Karthikeyan, Kishore K kishore.k.karthikeyan at intel.com
Wed May 20 14:23:09 PDT 2009


Formatted message: <a href="http://www.t10.org/cgi-bin/ac.pl?t=r&f=r0905205_f.htm">HTML-formatted message</a>

Thanks Brian for helping me understand the problem. I should not have
overlooked this important piece of information.
Fig 159 in sas2r15 threw me off guard because I saw the hot-plug timeout
followed by the COMINIT transmitted by PHY-B and I failed to check which
state it would be in when it is waiting for hotplug timer to expire.
Appreciate your help
Kishore
________________________________
From: Day, Brian [mailto:Brian.Day at lsi.com]
Sent: Wednesday, May 20, 2009 1:30 PM
To: Karthikeyan, Kishore K; t10 at t10.org
Subject: RE: SNW-3 SATA port selector confusion
Hi Kishore...
You're statement below here is correct:
"So while PHY-A is transmitting PHYCAP bit as part of SNW3, PHY-B is waiting
for hotplug timeout to expire."
Phy-B waiting for hot-plug to expire means it is in the SP1:OOB_AwaitCOMX
state.	Referring back to the SAS-1.1 spec for that state indicates that if a
COMWAKE is received in this state, that phy asserts the ATTACHED SATA PORT
SELECTOR bit.
I think this is the condition that the proposal tried to address.
Brian Day
LSI Corp.
________________________________
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of Karthikeyan,
Kishore K
Sent: Wednesday, May 20, 2009 1:06 PM
To: t10 at t10.org
Subject: RE: SNW-3 SATA port selector confusion
Hi
I hope atleast some people have got the chance to read through this email and
understand the issue at hand.
Again I will try to put the question in a different way to solicit some
response :)
If I don't implement this new arc in the SP statemachine (dc_idle detection
after SNW2), can I hit the discrepancy mentioned in this proposal (wrongly
detecting port selector attached) with valid speed negotiation scenarios? And
if I cannot hit this condition ever, do I really need to incorporate
unnecessary additional logic into the design?
Thanks
Kishore
________________________________
From: owner-t10 at t10.org [mailto:owner-t10 at t10.org] On Behalf Of Karthikeyan,
Kishore K
Sent: Monday, May 18, 2009 4:27 PM
To: t10 at t10.org
Subject: SNW-3 SATA port selector confusion
Please refer to the attached document
I have a question regarding this approved change to the SAS standard
(approved in July 2008)
The problem describes a scenario where PHY-B (which supports only SNW1) can
falsely detects a port selector due to the 1st COMWAKE it receives as part of
the PHY_CAPABILITIES bit of PHY-A (which supports only SNW3) in response to
PHY-A's COMINIT transmission after hotplug timeout.
Even though this problem looks real at first glance, can it ever really
happen? I say that because I think we are overlooking the fact that PHY-B
will restart OOB only after hotplug timeout which is 10ms minimum to a max of
500ms.
Lets look at the scenario in detail
If PHY-B detects that the SNW1 and SNW2 are both invalid, it will restart OOB
but ONLY after hotplug timeout (which can only be after a min of 10ms).
But PHY-A which supports only SNW3, will finish SNW-3 in RCDT (500us)+SNTT
(109us) = 610us and then restart OOB after hotplug timeout.
So while PHY-A is transmitting PHYCAP bit as part of SNW3, PHY-B is waiting
for hotplug timeout to expire. So by the time hotplug timeout of PHY-B
expires, PHY-A has already finished SNW3 and waiting for its own hotplug
timer to expire so that it can restart OOB.
So how can we ever hit the condition mentioned in this proposal? What am I
missing here?
Thanks in advance
Kishore
Intel Corporation



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