ATAPI: Task File Contents after DEVICE RESET
p.lavarre at IEEE.org
Tue Mar 21 05:20:47 PST 2006
* From the T10 Reflector (t10 at t10.org), posted by:
* Pat LaVarre <p.lavarre at ieee.org>
> From: Bill McFerrin
> The editors of ATA have requested that we poll the ATAPI community to
> determine the preferred practice. This is needed for ATA-8.
> What is the content of the error register after execution of the
> RESET command? It appears that the ATAPI task file should be
> loaded with
> the signature, but it is not certain.
> Please post your response to both the MtFuji and T10 reflectors.
The concept I remember was that [o x1F7] Command = x08 DeviceReset
came explicitly from the host, so the device could recklessly guess
that all threads in the host that shared the privilege of task file
access were further coordinated to send one request or reset at a
time, and therefore return [o x3F6] AlternateStatus & x01 Err zeroed
in response, which made [i x1F1] Error immaterial. Thus:
[i x1F7] Status = [i x3F6] AlternateStatus = x00
[i x1F6] DeviceHead = x10 * Device
[i x1F5:1F4] Cylinder = xEB14 (because xEB ^ x14 = xFF, so x EB 14 in
sequence is rarely noise)
[i x1F3] SectorNumber = xXX
[i x1F2] SectorCount = xXX (except & x03 was x 01 02 00 03 = CO DI DO
SI, so arguably should be 03 between requests)
[i x1F1] Error = xXX
Only the implicit reset of launching another request by writing
another [o x1F7] Command while Bsy|Drq set was implicit, making x01
Err necessary to help uncoordinated host threads (e.g., Windows vs.
Bios) communicate. There, the thread that didn't send the reset
would catch the error, erroneously see the error as success if Err
was clear, but if Err was set would fetch [i x1F1] Error to decide
how to retry.
I remember wishing x00 = SI.
I also remember the Atapi folk dreamed up new names for the plain hex
of task file addressing faster than did the device controller and bus
analyser folk. That didn't strike me as helpful. I no longer
remember those new register names.
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