SAS - PL_OC state machine - How many?

Seto, Pak-lung pak-lung.seto at intel.com
Wed May 14 14:44:08 PDT 2003


* From the T10 Reflector (t10 at t10.org), posted by:
* "Seto, Pak-lung" <pak-lung.seto at intel.com>
*
Mark,

Sometime, it is hard to see the problem until you start to think about how
to implment it.

Also, I want to confirm that - Am I missing something???? May be I am
smoking something that I missed the
basic I was not in SAS at the beginning.

Pak

-----Original Message-----
From: Evans, Mark [mailto:Mark_Evans at maxtor.com]
Sent: Wednesday, May 14, 2003 5:29 PM
To: 'Seto, Pak-lung'
Cc: 't10 at t10.org'
Subject: RE: SAS - PL_OC state machine - How many?


Well, Pak,

I don't know what to tell you.  Several of us put in literally hundreds of
hours each working on the words for the port layer clause in SAS.  Now,
after all of that time (including more hundreds of hours of effort for
letter ballot and letter ballot comment resolution), you think that what we
described would be difficult to implement in hardware.  You haven't said
that you found a technical issue with the draft standard, you've just said
that you think we didn't provide enough implementation guidance (which never
was our intent).

In the immortal words of George O. Penokie, "Bring in a proposal."

Regards,

Mark Evans
Maxtor Corporation

 -----Original Message-----
From: 	Seto, Pak-lung [mailto:pak-lung.seto at intel.com] 
Sent:	Wednesday, May 14, 2003 2:13 PM
To:	Evans, Mark; Seto, Pak-lung
Cc:	't10 at t10.org'
Subject:	RE: SAS - PL_OC state machine - How many?

Mark,

I know that, I already ignored how SAM defines the port.

Base on the description in clause 8 and the port layer example shown in
Figure 105, it only shows single PL_OC/Port layer.  I agree the standard
should leave the detail to the implementer.  But I don't the standard should
leave something like this be only implemenable by software and almost not
possible without a lot of pain for hardware implementation.

It is not the problem of one port layer per device or one port layer per
port - this is not important.  It is the problem of creating more PL_OC
state machines when the number of ports per device increase.  It is OK with
software port layer/PL_OC implementation but not for hardware.  This is the
same problem (actually worst) with the AL3 architecture.

Pak

-----Original Message-----
From: Evans, Mark [mailto:Mark_Evans at maxtor.com]
Sent: Wednesday, May 14, 2003 4:47 PM
To: 'Seto, Pak-lung'
Cc: 't10 at t10.org'
Subject: RE: SAS - PL_OC state machine - How many?


Hi Pak,

Architecturally, you can't have one port layer reside in two separate ports.
A port is a discrete SAM entity.  I'm not sure if the draft standard says it
in so many words, but Figure 23 (State machines for SAS devices) clearly
shows one port layer in one port.  However, the more I think about it, I
don't see what difference it makes if there is one port layer per device or
one per port (except for not working from a SCSI architecture standpoint).
If you ignore SCSI architecture, all of the port layer state machines could
reside in this amorphous port cloud in a device until PL_PM state machines
were assigned to PL_OC state machines by some magic of implementation.  It
could still fit together logically.

As is the intent with all SCSI standards, details (like how phys are
assigned to ports) are left to the implementer, and that IS easy to say.

Regards,

Mark Evans
Maxtor Corporation

 -----Original Message-----
From: 	Seto, Pak-lung [mailto:pak-lung.seto at intel.com] 
Sent:	Wednesday, May 14, 2003 1:09 PM
To:	Evans, Mark; Seto, Pak-lung
Cc:	't10 at t10.org'
Subject:	RE: SAS - PL_OC state machine - How many?

Mark

It is not clear from the spec that there is one port layer per port.
But it is the same hold true, how can hardware dynamically increase the
number
of port layer due to more port is created.  It is easy to say "all up to the
implementer".

Pak

-----Original Message-----
From: Evans, Mark [mailto:Mark_Evans at maxtor.com]
Sent: Wednesday, May 14, 2003 4:01 PM
To: 'Seto, Pak-lung'
Cc: 't10 at t10.org'
Subject: RE: SAS - PL_OC state machine - How many?


Hi Pak,

There is one port layer (and one PL_OC state machine) in each port.  There
is one PL_PM state machine for each phy.  The port has one SAS address.  The
phys in that port all report the one SAS address in their IDENTIFY frames.
How phys are aggregated into ports is not covered in the standard.  I could
see that simple devices that have a single phy permanently assigned to a
port could implement much of the port layer in hardware.  A hardware
implementation could be more difficult for a device that has more than one
phy that can be assigned dynamically to more than one port in a SAS device,
but it's all up to the implementer.

Regards,

Mark Evans
Maxtor Corporation

 -----Original Message-----
From: 	Seto, Pak-lung [mailto:pak-lung.seto at intel.com] 
Sent:	Wednesday, May 14, 2003 11:46 AM
To:	't10 at t10.org'
Cc:	Seto, Pak-lung
Subject:	SAS - PL_OC state machine - How many?

* From the T10 Reflector (t10 at t10.org), posted by:
* "Seto, Pak-lung" <pak-lung.seto at intel.com>
*
How many PL_OC state machines per PORT LAYER?

The way that is stated 8.2 of SAS v2g - "There is one PL_OC state machine
per port" - it seems match the state machine description.

What if I have a "chip" that can support multiple links (e.g 4 links) and
wide port configuration.  First, I would assume the "chip" will try to
attempt to make wide port link initialization (in this example - 4 links) by
sending out IDENTIFY frames on all 4 links with the same SAS address.  In
this case, if all the returning IDENTIFY frames has the same SAS address, a
4-links wide port is established - therefore - ONE PL_OC state machine.

What if the returning IDENTIFY frames has all different SAS address and
assume the "chip" will try to re-initialize the link by assing different SAS
addresses to each links (assuming to make config stay in one SAS domain).
After link initializaiton, 4 single link - 4 ports configuration is
established.  In this case - there will be 4 PL_OC state machines with "ONE"
port layer???

Does the standard expect the SAS port layer being implemented in firmware?
Otherwise, how does hardware implemented SAS port layer can dynamically
support various number of PL_OC state machines (not easy)?

In the SAS spec, it does not mention about this kind of situation and how
the PL_OC state machine or port layer handle this situation?  Did I
interpert the PL_OC state machine wrong?

Pak

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