SAS Rate match and misc

Elliott, Robert (Server Storage) Elliott at hp.com
Tue Oct 8 07:06:58 PDT 2002


* From the T10 Reflector (t10 at t10.org), posted by:
* "Elliott, Robert (Server Storage)" <Elliott at hp.com>
*
Thanks for your comments.

1. Figure 64 illustrates the case of 1.5Gbps transfer to 3.0Gbps. Is it
implied that the same concept of ALIGN insertion be used for 3.0Gbps ->
1.5Gbps or 6.0Gbps -> 1.5Gbps transfer? Below is a pictorial
representation of my perception of 6.0Gbps -> 1.5Gbps transfer.

Answer: the source has to know the link rate of the destination and all
intermediate physical links on the pathway (e.g. expander to expander
physical links).  It must pick the lowest common denominator, and stuff
extra ALIGNs in to accommodate that slowest physical link.  In your
example, the slowest link rate is at the destination port, so the 6.0
Gbps source adds 3 ALIGNs per dword.   (Note this is in addition to the
1 ALIGN per 2048 dwords required in general)

The source should the link rate based in its knowledge of the topology
(from SMP) rather than using trial-and-error.  However, trial-and-error
should also work.

2. "SSP" should be "STP" in 4.1.x
Answer: correct, that's a typo.

3. Field mismatches in DISCOVER.
Answer: PHY RESET PROBLEM belongs there but lost its bit assignment
recently. We'll find
a new home for it soon.  ATTACHED PHY IDENTIFIER is left over from days
past and will be removed.  ATTACHED DEVICE TYPE is TBD. The CURRENT
PHYSICAL LINK RATE field is cleaned up in sas-r02a.

4. Expander route slot/Expander route index unclear
Answer: See proposal 02-359r3 for completion of details on those fields.

5. REPORT PHY MARGIN SETTINGS size not multiple of 4
Answer: made a multiple of 4 in sas-r02a.

6. SMP link layer check for 24 bytes is too large
Answer: this is left over from when SMP frames had the same frame header
as SSP.  It now needs to be 4 bytes.


-- 
Rob Elliott, elliott at hp.com 
Industry Standard Server Storage Advanced Technology 
Hewlett-Packard 

-----Original Message-----
From: Yi-Chun Chen [mailto:ycchen at marvell.com] 
Sent: Monday, October 07, 2002 9:50 PM
To: T10
Subject: Rate match and misc


Hello , All : 
I have some question about the SAS rev0.2 list in the attached pdf file.

There are some issues and flow that are not clear, maybe someone else
has the same question. 
Look forward everyone's reply and discussion. Thanks 
  

------------------------------
Yi-Chun Chen
ycchen at marvell.com
Design Engineer 
------------------------------
Marvell Semiconductor Inc
Phone   : (408) 222-0817
Fax     : (408) 752-9025
Address : 700 First Ave, 
          Sunnyvale, CA 94089
Cube    : 4235
  
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