Inconsistent usage of "assertion and negation" in training pattern sectionof SPI-4

Gerry.Houlder at seagate.com Gerry.Houlder at seagate.com
Fri Mar 8 13:54:20 PST 2002


* From the T10 Reflector (t10 at t10.org), posted by:
* Gerry.Houlder at seagate.com
*
At least one engineer at my company is questioning the intent of some
wording in SPI-4, section 10.7.4. There is enough question that an
editorial change should be made. The question is which editorial change.

in section 10.7.4.2.2, After the words "Start of section A:", there is this
example of normal wording for an assertion and negation requirement:
...
8) simultaneously assert and negate REQ, P1, P_CRCA, and DB(15-0) signals
at the negotiated
transfer period 64 times, (e.g., (2 x 6,25 ns) x 64 = 800 ns at fast-160);
...

This example is representative of most phrases that include the words
"assert and negate". This usage of "64 times" describes 64 cycles (64
assertions and 64 negations) of the referenced signals.

Now compare that usage with section 10.7.4.3.3, after the words "SCSI
target ports shall begin pacing transfers by:"
...
1) simultaneously with the assertion of REQ the SCSI target port shall
begin asserting and negating
P1 at twice the negotiated transfer period (e.g., 12,5 ns for fast-160);
2) SCSI target port shall assert and negate P1 at least 8 times (e.g., (2 x
6,25 ns) x 8 = 100 ns at
fast-160); and
....

Note that this wording says "assert and negate ... 8 times" but the 100ns
timing value only allows for 4 assertions and 4 negations of P1 for the
frequency it must operate at. This is inconsistent editorial use of the
"assert and negate x times" phrase.

Now for the real test - Do we fix it with wording (A) or wording (B)? The
changed words are enclosed in <>.

(A) 2) SCSI target port shall assert and negate P1 at least 8 times (e.g.,
< (2 x 12,5 ns) x 8 = 200 ns > at
fast-160); and

(B) 2) SCSI target port shall assert and negate P1 at least < 4 > times
(e.g., < (2 x 12,5 ns) x 4 = 100 ns > at
fast-160); and

There might be people that will argue for (4 x 6,25ns) instead of (2 x
12.5ns) but at least these options will result in the same answer. The
basic choice here is whether P1 should idle for 8 cycles (the "8 times") or
for 4 cycles (the "100 ns" in the equation). I hope everyone comes to the
T10 meeting next week with the same answer.

I think (B) is what the committee intended. Anyone disagree with that? What
assumption has everyone's design made?

John, please add this item to the SPI working group agenda for Tuesday
3/12.

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